Lines Matching refs:Op
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
773 // = op c3, ..., f2
1098 SDValue Op;
1100 Op = DAG.getConstantFP(0, EltVT);
1102 Op = DAG.getConstant(0, EltVT);
1103 Ops.assign(NumElements, Op);
1396 assert(Opc == Instruction::And && "Unknown merge op!");
2658 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2665 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2673 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2681 // FPTrunc is never a no-op cast, no need to check
2689 // FPExt is never a no-op cast, no need to check
2696 // FPToUI is never a no-op cast, no need to check
2703 // FPToSI is never a no-op cast, no need to check
2710 // UIToFP is never a no-op cast, no need to check
2717 // SIToFP is never a no-op cast, no need to check
2725 // We can either truncate, zero extend, or no-op, accordingly.
2733 // We can either truncate, zero extend, or no-op, accordingly.
2744 // either a BITCAST or a no-op.
3500 SDValue Op = getValue(I.getArgOperand(i));
3501 assert(TLI.isTypeLegal(Op.getValueType()) &&
3503 Ops.push_back(Op);
3562 /// Op = (Op & 0x007fffff) | 0x3f800000;
3564 /// where Op is the hexidecimal representation of floating point value.
3566 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3567 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3576 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3578 /// where Op is the hexidecimal representation of floating point value.
3580 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3582 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3599 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3604 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3617 SDValue Op = getValue(I.getArgOperand(0));
3624 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3743 SDValue Op = getValue(I.getArgOperand(0));
3744 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3853 SDValue Op = getValue(I.getArgOperand(0));
3854 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3962 SDValue Op = getValue(I.getArgOperand(0));
3963 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4064 SDValue Op = getValue(I.getArgOperand(0));
4066 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4070 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4190 SDValue Op = getValue(I.getArgOperand(1));
4197 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4674 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4675 setValue(&I, Op);
4676 DAG.setRoot(Op.getValue(1));
4699 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4700 DAG.setRoot(Op.getValue(1));
4701 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4763 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4766 setValue(&I, Op.getValue(0));
4767 DAG.setRoot(Op.getValue(1));
4931 SDValue Op = getRoot();
4934 &Op, 1);
4963 SDValue Op = getRoot();
4965 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
6341 SDValue Op = SDValue(Args[i].Node.getNode(),
6383 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6491 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6498 SDValue Op = getNonRegisterValue(V);
6499 assert((Op.getOpcode() != ISD::CopyFromReg ||
6500 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6506 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
