Lines Matching refs:N0
1908 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1924 if (isa<ConstantSDNode>(N0.getNode()))
1925 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1933 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1934 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1935 N0.getOperand(1).getOpcode() == ISD::Constant) {
1937 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1939 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1949 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1950 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1955 SDValue CTPOP = N0;
1957 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1958 CTPOP = N0.getOperand(0);
1961 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1980 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1982 unsigned MinBits = N0.getValueSizeInBits();
1984 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1986 MinBits = N0->getOperand(0).getValueSizeInBits();
1987 PreZExt = N0->getOperand(0);
1988 } else if (N0->getOpcode() == ISD::AND) {
1990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1993 PreZExt = N0->getOperand(0);
1995 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1999 PreZExt = N0;
2019 N0.getOpcode() == ISD::AND && C1 == 0 &&
2020 N0.getNode()->hasOneUse() &&
2021 isa<LoadSDNode>(N0.getOperand(0)) &&
2022 N0.getOperand(0).getNode()->hasOneUse() &&
2023 isa<ConstantSDNode>(N0.getOperand(1))) {
2024 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2028 unsigned origWidth = N0.getValueType().getSizeInBits();
2035 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2074 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2075 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2109 EVT newVT = N0.getOperand(0).getValueType();
2113 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2121 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2123 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2125 EVT ExtDstTy = N0.getValueType();
2134 EVT Op0Ty = N0.getOperand(0).getValueType();
2136 ZextOp = N0.getOperand(0);
2139 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2154 if (N0.getOpcode() == ISD::SETCC &&
2155 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2158 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2160 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2162 N0.getOperand(0).getValueType().isInteger());
2163 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2166 if ((N0.getOpcode() == ISD::XOR ||
2167 (N0.getOpcode() == ISD::AND &&
2168 N0.getOperand(0).getOpcode() == ISD::XOR &&
2169 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2170 isa<ConstantSDNode>(N0.getOperand(1)) &&
2171 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2174 unsigned BitWidth = N0.getValueSizeInBits();
2175 if (DAG.MaskedValueIsZero(N0,
2180 if (N0.getOpcode() == ISD::XOR)
2181 Val = N0.getOperand(0);
2183 assert(N0.getOpcode() == ISD::AND &&
2184 N0.getOperand(0).getOpcode() == ISD::XOR);
2186 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2187 N0.getOperand(0).getOperand(0),
2188 N0.getOperand(1));
2197 SDValue Op0 = N0;
2242 return DAG.getSetCC(dl, VT, N0,
2250 return DAG.getSetCC(dl, VT, N0,
2266 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2269 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2273 return DAG.getSetCC(dl, VT, N0,
2274 DAG.getConstant(MinVal, N0.getValueType()),
2278 return DAG.getSetCC(dl, VT, N0,
2279 DAG.getConstant(MaxVal, N0.getValueType()),
2288 return DAG.getSetCC(dl, VT, N0,
2298 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2303 (VT == N0.getValueType() ||
2304 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2305 N0.getOpcode() == ISD::AND)
2307 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2309 getPointerTy() : getShiftAmountTy(N0.getValueType());
2314 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2322 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2329 if (isa<ConstantFPSDNode>(N0.getNode())) {
2331 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2354 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2358 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2365 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2366 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2368 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2369 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2371 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2372 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2374 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2375 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2378 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2379 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2381 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2382 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2384 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2385 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2387 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2388 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2394 if (N0 == N1) {
2396 if (N0.getValueType().isInteger())
2407 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2411 N0.getValueType().isInteger()) {
2412 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2413 N0.getOpcode() == ISD::XOR) {
2415 if (N0.getOpcode() == N1.getOpcode()) {
2416 if (N0.getOperand(0) == N1.getOperand(0))
2417 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2418 if (N0.getOperand(1) == N1.getOperand(1))
2419 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2420 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2422 if (N0.getOperand(0) == N1.getOperand(1))
2423 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2425 if (N0.getOperand(1) == N1.getOperand(0))
2426 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2432 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2434 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2435 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2438 N0.getValueType()), Cond);
2442 if (N0.getOpcode() == ISD::XOR)
2445 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2447 DAG.getSetCC(dl, VT, N0.getOperand(0),
2450 N0.getValueType()),
2455 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2456 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2458 DAG.getSetCC(dl, VT, N0.getOperand(1),
2461 N0.getValueType()),
2468 if (N0.getOperand(0) == N1)
2469 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2470 DAG.getConstant(0, N0.getValueType()), Cond);
2471 if (N0.getOperand(1) == N1) {
2472 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2473 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2474 DAG.getConstant(0, N0.getValueType()), Cond);
2475 else if (N0.getNode()->hasOneUse()) {
2476 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2483 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2491 if (N1.getOperand(0) == N0) {
2494 } else if (N1.getOperand(1) == N0) {
2501 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2502 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2514 if (N0.getOpcode() == ISD::AND)
2515 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2519 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2523 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2524 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2526 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2534 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2538 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2539 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2544 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2548 Temp = DAG.getNOT(dl, N0, MVT::i1);
2549 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2556 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2562 Temp = DAG.getNOT(dl, N0, MVT::i1);
2563 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2570 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2575 DCI.AddToWorklist(N0.getNode());
2577 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2579 return N0;
