Lines Matching refs:MIB
655 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
656 MIB.addReg(SrcReg, getKillRegState(KillSrc));
658 MIB.addReg(SrcReg, getKillRegState(KillSrc));
659 AddDefaultPred(MIB);
690 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
694 return MIB.addReg(Reg, State);
697 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
698 return MIB.addReg(Reg, State, SubIdx);
766 MachineInstrBuilder MIB =
770 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
771 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
772 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
773 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
780 MachineInstrBuilder MIB =
784 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
785 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
786 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
787 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
788 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
789 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
790 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
791 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
910 MachineInstrBuilder MIB =
914 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
915 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
916 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
917 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
918 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
925 MachineInstrBuilder MIB =
929 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
930 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
931 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
932 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
933 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
934 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
935 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
936 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
937 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
1070 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1072 return &*MIB;
1138 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1141 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
