Lines Matching refs:Opcode
55 unsigned MLxOpc; // MLA / MLS opcode
56 unsigned MulOpc; // Expanded multiplication opcode
57 unsigned AddSubOpc; // Expanded add / sub opcode
1041 // Change the opcode and operands.
1125 unsigned Opcode = Orig->getOpcode();
1126 switch (Opcode) {
1138 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1166 int Opcode = MI0->getOpcode();
1167 if (Opcode == ARM::t2LDRpci ||
1168 Opcode == ARM::t2LDRpci_pic ||
1169 Opcode == ARM::tLDRpci ||
1170 Opcode == ARM::tLDRpci_pic ||
1171 Opcode == ARM::MOV_ga_dyn ||
1172 Opcode == ARM::MOV_ga_pcrel ||
1173 Opcode == ARM::MOV_ga_pcrel_ldr ||
1174 Opcode == ARM::t2MOV_ga_dyn ||
1175 Opcode == ARM::t2MOV_ga_pcrel) {
1176 if (MI1->getOpcode() != Opcode)
1186 if (Opcode == ARM::MOV_ga_dyn ||
1187 Opcode == ARM::MOV_ga_pcrel ||
1188 Opcode == ARM::MOV_ga_pcrel_ldr ||
1189 Opcode == ARM::t2MOV_ga_dyn ||
1190 Opcode == ARM::t2MOV_ga_pcrel)
1212 } else if (Opcode == ARM::PICLDR) {
1213 if (MI1->getOpcode() != Opcode)
1453 llvm_unreachable("Unknown unconditional branch opcode!");
1539 unsigned Opcode = MI.getOpcode();
1545 if (Opcode == ARM::INLINEASM)
1548 if (Opcode == ARM::ADDri) {
1637 // Attempt to fold address comp. if opcode has offset bits
2504 if (isZeroCost(DefMCID.Opcode))
2698 unsigned Opcode = Node->getMachineOpcode();
2699 switch (Opcode) {
2701 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2753 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2756 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
