Lines Matching refs:MIB
417 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
433 MIB.addOperand(MI.getOperand(OpIdx++));
436 MIB.addOperand(MI.getOperand(OpIdx++));
437 MIB.addOperand(MI.getOperand(OpIdx++));
440 MIB.addOperand(MI.getOperand(OpIdx++));
450 MIB.addOperand(MI.getOperand(OpIdx++));
451 MIB.addOperand(MI.getOperand(OpIdx++));
458 MIB.addOperand(MO);
461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
462 TransferImpOps(MI, MIB, MIB);
465 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
481 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
485 MIB.addOperand(MI.getOperand(OpIdx++));
488 MIB.addOperand(MI.getOperand(OpIdx++));
489 MIB.addOperand(MI.getOperand(OpIdx++));
492 MIB.addOperand(MI.getOperand(OpIdx++));
498 MIB.addReg(D0).addReg(D1);
500 MIB.addReg(D2);
502 MIB.addReg(D3);
505 MIB.addOperand(MI.getOperand(OpIdx++));
506 MIB.addOperand(MI.getOperand(OpIdx++));
509 MIB->addRegisterKilled(SrcReg, TRI, true);
510 TransferImpOps(MI, MIB, MIB);
513 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
530 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
552 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
554 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
556 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
558 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
562 MIB.addOperand(MI.getOperand(OpIdx++));
565 MIB.addOperand(MI.getOperand(OpIdx++));
566 MIB.addOperand(MI.getOperand(OpIdx++));
569 MIB.addOperand(MI.getOperand(OpIdx++));
579 MIB.addReg(D0, SrcFlags);
581 MIB.addReg(D1, SrcFlags);
583 MIB.addReg(D2, SrcFlags);
585 MIB.addReg(D3, SrcFlags);
588 MIB.addImm(Lane);
592 MIB.addOperand(MI.getOperand(OpIdx++));
593 MIB.addOperand(MI.getOperand(OpIdx++));
597 MIB.addOperand(MO);
600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
601 TransferImpOps(MI, MIB, MIB);
612 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
616 MIB.addOperand(MI.getOperand(OpIdx++));
618 MIB.addOperand(MI.getOperand(OpIdx++));
624 MIB.addReg(D0).addReg(D1);
626 MIB.addReg(D2);
628 MIB.addReg(D3);
631 MIB.addOperand(MI.getOperand(OpIdx++));
634 MIB.addOperand(MI.getOperand(OpIdx++));
635 MIB.addOperand(MI.getOperand(OpIdx++));
638 MIB->addRegisterKilled(SrcReg, TRI, true);
639 TransferImpOps(MI, MIB, MIB);
871 MachineInstrBuilder MIB =
877 TransferImpOps(MI, MIB, MIB);
883 MachineInstrBuilder MIB =
888 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
889 TransferImpOps(MI, MIB, MIB);
975 MachineInstrBuilder MIB =
984 MIB.addOperand(MI.getOperand(OpIdx++));
987 MIB.addOperand(MI.getOperand(OpIdx++));
988 MIB.addOperand(MI.getOperand(OpIdx++));
993 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
997 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
998 TransferImpOps(MI, MIB, MIB);
1005 MachineInstrBuilder MIB =
1014 MIB.addOperand(MI.getOperand(OpIdx++));
1017 MIB.addOperand(MI.getOperand(OpIdx++));
1018 MIB.addOperand(MI.getOperand(OpIdx++));
1023 MIB.addReg(D0).addReg(D1);
1026 MIB->addRegisterKilled(SrcReg, TRI, true);
1028 TransferImpOps(MI, MIB, MIB);
1036 MachineInstrBuilder MIB =
1046 MIB.addOperand(MI.getOperand(OpIdx++));
1047 MIB.addReg(DReg);
1050 MIB.addImm(Lane);
1052 MIB.addOperand(MI.getOperand(OpIdx++));
1053 MIB.addOperand(MI.getOperand(OpIdx++));
1055 TransferImpOps(MI, MIB, MIB);
