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Lines Matching refs:AddDefaultPred

203     AddDefaultCC(AddDefaultPred(MIB));
261       AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
272       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
274       AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
278       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
297       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
368           AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
378           AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
586         AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
596       AddDefaultPred(MIB);
648         AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
673       AddDefaultPred(MIB);