Lines Matching full:i64
109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
238 // i64 conversions are done via library routines even when generating VFP
250 // i64 conversions are done via library routines even when generating VFP
549 // i64 operation support.
550 setOperationAction(ISD::MUL, MVT::i64, Expand);
563 setOperationAction(ISD::SRL, MVT::i64, Custom);
564 setOperationAction(ISD::SRA, MVT::i64, Custom);
627 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
628 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
629 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
630 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
631 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
632 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
633 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
670 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
672 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
2587 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3208 /// expand a bit convert where either the source or destination type is i64 to
3209 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3217 // This function is only supposed to be called for i64 types, either as the
3221 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3222 "ExpandBITCAST called for non-i64 type");
3224 // Turn i64->f64 into VMOVDRR.
3225 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3234 // Turn f64->i64 into VMOVRRD.
3235 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3238 // Merge the pieces into a single i64 value.
3239 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3248 /// not support i64 elements, so sometimes the zero vectors will need to be
3400 // We can get here for a node like i32 = ISD::SHL i32, i64
3401 if (VT != MVT::i64)
3429 // Merge the pieces into a single i64 value.
3430 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3661 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4032 // registers are defined to use, and since i64 is not legal.
4428 // registers are defined to use, and since i64 is not legal.
4908 assert (Node->getValueType(0) == MVT::i64 &&
4909 "Only know how to expand i64 atomics");
4930 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
4933 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6554 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
6618 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7074 // Bitcast an i64 store extracted from a vector to f64.
7075 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7099 if (StVal.getValueType() != MVT::i64 ||
7112 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
7125 /// i64 vector to have f64 elements, since the value can then be loaded
7142 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
7144 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
7152 // Load i64 elements as f64 values so that type legalization does not split
7155 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
7175 // Bitcast an i64 load inserted into a vector to f64.
7176 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7179 if (VT.getVectorElementType() != MVT::i64 ||
8222 case MVT::i64:
8280 case MVT::i64:
8878 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8904 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8916 Info.memVT = MVT::i64;
8927 Info.memVT = MVT::i64;
