Lines Matching refs:N0
4604 SDNode *N0 = N->getOperand(0).getNode();
4606 return N0->hasOneUse() && N1->hasOneUse() &&
4607 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4615 SDNode *N0 = N->getOperand(0).getNode();
4617 return N0->hasOneUse() && N1->hasOneUse() &&
4618 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4628 SDNode *N0 = Op.getOperand(0).getNode();
4632 bool isN0SExt = isSignExtended(N0, DAG);
4637 bool isN0ZExt = isZeroExtended(N0, DAG);
4644 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4647 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4651 std::swap(N0, N1);
4672 Op0 = SkipExtension(N0, DAG);
4687 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4688 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4690 return DAG.getNode(N0->getOpcode(), DL, VT,
4727 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4732 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4734 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4750 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4751 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4754 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4755 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4758 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4759 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4760 return N0;
4769 SDValue N0 = Op.getOperand(0);
4774 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4777 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4781 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4786 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4789 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4790 N0 = LowerCONCAT_VECTORS(N0, DAG);
4792 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4793 return N0;
4795 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4804 SDValue N0 = Op.getOperand(0);
4809 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4812 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4816 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4821 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4824 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4825 N0 = LowerCONCAT_VECTORS(N0, DAG);
4827 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4829 N0);
4830 return N0;
4836 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4838 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4859 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4860 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4863 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4864 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4867 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4868 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4869 return N0;
6541 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6548 || N0.getOpcode() != ISD::BUILD_VECTOR
6558 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
6564 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6566 SDValue Vec = N0->getOperand(0)->getOperand(0);
6573 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
6574 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6577 SDValue ExtVec0 = N0->getOperand(i);
6629 /// operands N0 and N1. This is a helper for PerformADDCombine that is
6632 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6637 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
6642 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6643 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
6654 SDValue N0 = N->getOperand(0);
6658 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
6663 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
6670 SDValue N0 = N->getOperand(0);
6675 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
6697 SDValue N0 = N->getOperand(0);
6699 unsigned Opcode = N0.getOpcode();
6706 std::swap(N0, N1);
6711 SDValue N00 = N0->getOperand(0);
6712 SDValue N01 = N0->getOperand(1);
6840 SDValue N0 = N->getOperand(0);
6841 if (N0.getOpcode() != ISD::AND)
6852 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
6864 N0->getOperand(1), N0->getOperand(0),
6892 SDValue N00 = N0.getOperand(0);
6897 SDValue MaskOp = N0.getOperand(1);
7541 SDValue N0 = Op->getOperand(0);
7553 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
7844 SDValue N0 = N->getOperand(0);
7850 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7851 SDValue Vec = N0.getOperand(0);
7852 SDValue Lane = N0.getOperand(1);
7854 EVT EltVT = N0.getValueType();
