Lines Matching refs:Opcode
811 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
812 switch (Opcode) {
3024 assert(0 && "Invalid opcode!");
3049 assert(0 && "Invalid opcode!");
3074 assert(0 && "Invalid opcode!");
3378 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4268 default: llvm_unreachable("Unknown shuffle opcode!");
4602 unsigned Opcode = N->getOpcode();
4603 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4613 unsigned Opcode = N->getOpcode();
4614 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6099 default: llvm_unreachable("unexpected opcode!");
6217 // true/false values to select between, and a branch opcode to use.
6327 // true/false values to select between, and a branch opcode to use.
6427 "converted opcode should be the same except for cc_out");
6699 unsigned Opcode = N0.getOpcode();
6700 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6701 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
6702 Opcode = N1.getOpcode();
6703 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6704 Opcode != ISD::FADD && Opcode != ISD::FSUB)
6713 return DAG.getNode(Opcode, DL, VT,
7276 // Find the new opcode for the updating load/store.
7317 default: assert(0 && "unexpected opcode for Neon base update");
7625 /// operand of a vector shift right operation. For a shift opcode, the value
7733 // Opcode already set above.
7820 default: llvm_unreachable("unexpected shift opcode");
7864 default: llvm_unreachable("unexpected opcode");
7902 unsigned Opcode = 0;
7934 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
7956 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
7960 if (!Opcode)
7962 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
