Lines Matching refs:getOpcode
1594 if (Arg.getOpcode() == ISD::CopyFromReg) {
1864 if (Use->getOpcode() == ISD::CopyToReg) {
1866 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1870 getOpcode() != ISD::CopyToReg)
1875 } else if (Use->getOpcode() == ISD::BITCAST) {
1880 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1895 if (UI->getOpcode() == ISD::CopyToReg) {
1901 if (UI->getOpcode() != ARMISD::RET_FLAG)
2638 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2724 unsigned Opc = Cmp.getOpcode();
2731 Opc = Cmp.getOpcode();
2752 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3022 switch (Op.getOpcode()) {
3047 switch (Op.getOpcode()) {
3072 switch (Op.getOpcode()) {
3094 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3095 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3272 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3274 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3309 assert(Op.getOpcode() == ISD::SHL_PARTS);
3372 if (N->getOpcode() == ISD::SHL)
3377 assert((N->getOpcode() == ISD::SRA ||
3378 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3387 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3404 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3423 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3510 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3513 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3972 if (V.getOpcode() == ISD::UNDEF)
4059 if (V.getOpcode() == ISD::UNDEF)
4061 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4160 if (Entry.getOpcode() == ISD::UNDEF) {
4320 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4353 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4481 if (Op0.getOpcode() != ISD::UNDEF)
4485 if (Op1.getOpcode() != ISD::UNDEF)
4499 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4502 BVN->getOpcode() != ISD::BUILD_VECTOR)
4523 if (N->getOpcode() != ISD::BUILD_VECTOR)
4549 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4559 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4569 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4577 if (N->getOpcode() == ISD::BITCAST) {
4579 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4586 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4602 unsigned Opcode = N->getOpcode();
4613 unsigned Opcode = N->getOpcode();
4690 return DAG.getNode(N0->getOpcode(), DL, VT,
4878 switch (Op.getOpcode()) {
4938 switch (Op.getOpcode()) {
5000 switch (N->getOpcode()) {
6053 switch (MI->getOpcode()) {
6073 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
6098 switch (MI->getOpcode()) {
6275 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
6407 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
6420 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
6485 unsigned Opc = N->getOpcode();
6486 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
6495 if (CCOp.getOpcode() == ISD::SETCC)
6504 if (LHS.getOpcode() == ISD::Constant &&
6508 RHS.getOpcode() == ISD::Constant &&
6548 || N0.getOpcode() != ISD::BUILD_VECTOR
6549 || N1.getOpcode() != ISD::BUILD_VECTOR)
6564 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6574 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6575 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6642 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6674 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
6699 unsigned Opcode = N0.getOpcode();
6702 Opcode = N1.getOpcode();
6841 if (N0.getOpcode() != ISD::AND)
6846 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
6923 } else if (N1.getOpcode() == ISD::AND) {
6968 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
6993 if (N1.getOpcode() == ISD::AND) {
7016 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
7023 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
7058 if (Op0.getOpcode() == ISD::BITCAST)
7060 if (Op1.getOpcode() == ISD::BITCAST)
7062 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
7081 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
7100 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7212 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
7213 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
7219 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
7220 Concat1Op1.getOpcode() != ISD::UNDEF)
7258 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
7259 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
7267 if (User->getOpcode() != ISD::ADD ||
7316 switch (N->getOpcode()) {
7395 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
7423 if (User->getOpcode() != ARMISD::VDUPLANE ||
7476 while (Op.getOpcode() == ISD::BITCAST)
7478 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
7537 Op.getOpcode() != ISD::FMUL)
7543 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
7545 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7571 unsigned OpOpcode = Op.getNode()->getOpcode();
7581 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7598 while (Op.getOpcode() == ISD::BITCAST)
7819 switch (N->getOpcode()) {
7831 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
7850 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7863 switch (N->getOpcode()) {
7969 if (Cmp.getOpcode() != ARMISD::CMPZ)
8032 switch (N->getOpcode()) {
8324 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8333 assert(Ptr->getOpcode() == ISD::ADD);
8339 isInc = (Ptr->getOpcode() == ISD::ADD);
8347 assert(Ptr->getOpcode() == ISD::ADD);
8355 if (Ptr->getOpcode() == ISD::ADD) {
8358 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
8369 isInc = (Ptr->getOpcode() == ISD::ADD);
8383 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8390 assert(Ptr->getOpcode() == ISD::ADD);
8395 isInc = Ptr->getOpcode() == ISD::ADD;
8481 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
8501 switch (Op.getOpcode()) {
