Lines Matching full:pseudo
390 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
1540 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1836 // at least be a pseudo instruction expanding to the predicated version
1947 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2526 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
3071 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3076 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3897 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3922 // Pseudo i64 compares for some floating point compares.
4028 // Pseudo isntruction that combines movs + predicated rsbmi
4597 // This is a pseudo inst so that we can get the encoding right,
4619 // These are pseudo-instructions and are lowered to individual MC-insts, so
4649 // eh.sjlj.dispatchsetup pseudo-instruction.
4650 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4651 // handled when the pseudo is expanded (which happens before any passes
4673 // This is a single pseudo instruction, the benefit is that it can be remat'd
4681 // Pseudo instruction that combines movw + movt + add pc (if PIC).
