Lines Matching defs:Opcode
91 int Offset, unsigned Base, bool BaseKill, int Opcode,
102 int Opcode,
109 int Opcode, unsigned Size,
132 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
133 switch (Opcode) {
134 default: llvm_unreachable("Unhandled opcode!");
213 AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
214 switch (Opcode) {
215 default: llvm_unreachable("Unhandled opcode!");
292 int Opcode, ARMCC::CondCodes Pred,
302 bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
312 // Check if this is a supported opcode before we insert instructions to
314 if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return false;
323 if (isi32Load(Opcode))
351 bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
352 Opcode == ARM::VLDRD);
353 Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
354 if (!Opcode) return false;
355 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
372 int Opcode,
407 if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode,
439 unsigned Base, int Opcode, unsigned Size,
443 bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
458 switch (Opcode) {
493 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
494 MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
505 Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
594 default: llvm_unreachable("Unhandled opcode!");
690 int Opcode = MI->getOpcode();
700 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(Opcode);
746 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
784 default: llvm_unreachable("Unhandled opcode!");
810 default: llvm_unreachable("Unhandled opcode!");
826 int Opcode = MI->getOpcode();
828 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
829 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
830 bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
831 if (isi32Load(Opcode) || isi32Store(Opcode))
837 bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
865 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
884 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
984 int Opcode = MI->getOpcode();
985 switch (Opcode) {
1021 int Opcode = MI->getOpcode();
1022 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
1026 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
1027 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
1028 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
1029 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
1071 unsigned Opcode = MI->getOpcode();
1072 if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||
1073 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {
1082 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
1083 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
1202 int Opcode = MBBI->getOpcode();
1220 Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());
1224 CurrOpc = Opcode;
1237 if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
1358 unsigned Opcode = PrevMI->getOpcode();
1359 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
1360 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
1361 Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
1366 assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||
1367 Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
1515 unsigned Opcode = Op0->getOpcode();
1516 if (Opcode == ARM::LDRi12)
1518 else if (Opcode == ARM::STRi12)
1520 else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
1524 } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {
1618 unsigned Opcode = Op->getOpcode();
1619 if (LastOpcode && Opcode != LastOpcode)
1630 LastOpcode = Opcode;
