Lines Matching refs:Registers
276 SmallVector<unsigned, 8> Registers;
316 // A vector register list is a sequential list of 1 to 4 registers.
402 Registers = o.Registers;
484 return Registers;
779 // Thumb reg+reg addressing is simple. Just two registers, a base and
1722 Op->Registers.push_back(I->first);
1723 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1983 // Also check for an index operand. This is only legal for vector registers,
2131 // Also check for an index operand. This is only legal for vector registers,
2360 // The reglist instructions have at most 16 registers, so reserve
2362 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2364 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2388 // Add all the registers in the range to the register list.
2391 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2413 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2421 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3926 // If both registers are low, we're in an IT block, and the immediate is
3947 // If the registers aren't low regs, the destination reg isn't the
4185 // return 'true' if register list contains non-low GPR registers,
4321 "registers must be in range r0-r7");
4346 "registers must be in range r0-r7 or pc");
4353 "registers must be in range r0-r7 or lr");
4360 "registers must be in range r0-r7");
4442 // If the register list contains any high registers, or if the writeback
4466 // If the register list contains any high registers, we need to use
4609 // Some high-register supporting Thumb1 encodings only allow both registers
