Lines Matching refs:MIB
129 MachineInstrBuilder MIB =
132 MIB = AddDefaultT1CC(MIB);
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
137 AddDefaultPred(MIB);
241 const MachineInstrBuilder MIB =
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
262 MIB = AddDefaultT1CC(MIB);
263 MIB.addReg(DestReg).addImm(ThisVal);
264 MIB = AddDefaultPred(MIB);
265 MIB.setMIFlags(MIFlags);
268 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
270 MIB = AddDefaultT1CC(MIB);
271 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
272 MIB = AddDefaultPred(MIB);
273 MIB.setMIFlags(MIFlags);
419 MachineInstrBuilder MIB(&MI);
430 MachineInstrBuilder MIB(&MI);
431 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
459 MachineInstrBuilder MIB(&MI);
460 MIB).addReg(FrameReg).addImm(Mask));
703 MachineInstrBuilder MIB(&MI);
704 AddDefaultPred(MIB);
