Lines Matching refs:VA
182 CCValAssign &VA = ArgLocs[i];
184 if (VA.isRegLoc()) {
185 EVT RegVT = VA.getLocVT();
186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
188 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
192 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
198 if (VA.getLocInfo() == CCValAssign::SExt)
200 DAG.getValueType(VA.getValVT()));
201 else if (VA.getLocInfo() == CCValAssign::ZExt)
203 DAG.getValueType(VA.getValVT()));
205 if (VA.getLocInfo() != CCValAssign::Full)
206 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
210 assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
211 unsigned ObjSize = VA.getLocVT().getStoreSize();
212 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
214 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
251 CCValAssign &VA = RVLocs[i];
252 assert(VA.isRegLoc() && "Can only return in registers!");
256 switch (VA.getLocInfo()) {
260 Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
263 Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
266 Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
269 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
309 CCValAssign &VA = ArgLocs[i];
313 switch (VA.getLocInfo()) {
317 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
320 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
323 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
329 if (VA.isRegLoc()) {
330 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
332 assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
333 int Offset = VA.getLocMemOffset();
335 assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
