Lines Matching full:i64
110 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
123 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
173 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
198 setOperationAction(ISD::SREM, MVT::i64, Expand);
199 setOperationAction(ISD::UREM, MVT::i64, Expand);
200 setOperationAction(ISD::SDIV, MVT::i64, Expand);
201 setOperationAction(ISD::UDIV, MVT::i64, Expand);
202 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
203 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
249 setOperationAction(ISD::SHL, MVT::i64, Legal);
250 setOperationAction(ISD::SRL, MVT::i64, Legal);
251 setOperationAction(ISD::SRA, MVT::i64, Legal);
253 // Custom lower i8, i32 and i64 multiplications
256 setOperationAction(ISD::MUL, MVT::i64, Legal);
272 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
273 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
274 setOperationAction(ISD::MULHU, MVT::i64, Expand);
275 setOperationAction(ISD::MULHS, MVT::i64, Expand);
277 // Need to custom handle (some) common i8, i64 math ops
279 setOperationAction(ISD::ADD, MVT::i64, Legal);
281 setOperationAction(ISD::SUB, MVT::i64, Legal);
286 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
291 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
297 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
303 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
311 setOperationAction(ISD::SELECT, MVT::i64, Legal);
316 setOperationAction(ISD::SETCC, MVT::i64, Legal);
319 // Custom lower i128 -> i64 truncates
320 setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
322 // Custom lower i32/i64 -> i128 sign extend
333 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
334 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
341 // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
349 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
382 // Cell SPU has instructions for converting between i64 and fp.
383 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
384 setOperationAction(ISD::SINT_TO_FP, MVT::i64
386 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
390 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
713 // if there is no highpart (i.e. value is i64 and offset is 4), this
1106 SDValue T = DAG.getConstant(dbits, MVT::i64);
1164 case MVT::i64:
1323 case MVT::i64:
1533 if (ValueType == MVT::i64) {
1555 if (ValueType == MVT::i64) {
1578 if (ValueType == MVT::i64) {
1625 || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
1644 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
1694 SDValue T = DAG.getConstant(f64val, MVT::i64);
1869 } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
1976 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1993 case MVT::i64:
2021 else if (VT == MVT::i64 && EltNo >= 2)
2022 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
2024 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
2025 // i32 and i64: Element 0 is the preferred slot
2049 case MVT::i64:
2149 case MVT::i64:
2459 case MVT::i64:
2469 All conversions to i64 are expanded to a libcall.
2478 || OpVT == MVT::i64) {
2479 // Convert f32 / f64 to i32 / i64 via libcall.
2495 All conversions from i64 are expanded to a libcall.
2504 || Op0VT == MVT::i64) {
2505 // Convert i32, i64 to f64 via libcall:
2535 EVT IntVT(MVT::i64);
2695 if (Op0VT == MVT::i128 && simpleVT == MVT::i64) {
2716 * Emit the instruction sequence for i64/i32 -> i128 sign extend. The basic
2719 * the leftmost words and the i64/i32 into the rightmost words using shufb.
2743 // the type to extend from needs to be i64 or i32.
2744 assert((OpVT == MVT::i128 && (Op0VT == MVT::i64 || Op0VT == MVT::i32)) &&
2750 unsigned mask2 = Op0VT == MVT::i64 ? 0x00010203 : 0x10101010; // byte 8 - 11
2751 unsigned mask3 = Op0VT == MVT::i64 ? 0x04050607 : 0x00010203; // byte 12 - 15
2760 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
2817 // i8, i64 math ops:
3155 if (VT == MVT::i64)
