Lines Matching refs:getOpcode
593 if (basePtr.getOpcode() == ISD::ADD
611 } else if ((basePtr.getOpcode() == SPUISD::AFormAddr)
612 || (basePtr.getOpcode() == SPUISD::IndirectAddr
613 && basePtr.getOperand(0).getOpcode() == SPUISD::Hi
614 && basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) {
633 if (basePtr.getOpcode() == ISD::ADD) {
800 if (basePtr.getOpcode() == ISD::ADD
827 if (basePtr.getOpcode() == ISD::ADD) {
873 && (theValue.getOpcode() == ISD::AssertZext
874 || theValue.getOpcode() == ISD::AssertSext)) {
1510 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1841 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1959 if (Op0.getNode()->getOpcode() == ISD::Constant) {
2177 if (IdxOp.getOpcode() != ISD::UNDEF) {
2316 if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
2317 if (ConstVec.getNode()->getOpcode() == ISD::BITCAST) {
2322 if (ConstVec.getNode()->getOpcode() == ISD::BITCAST) {
2328 if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
2345 return DAG.getNode(Op.getNode()->getOpcode(), dl, VT, Arg,
2481 (Op.getOpcode() == ISD::FP_TO_SINT)
2507 (Op.getOpcode() == ISD::SINT_TO_FP)
2788 unsigned Opc = (unsigned) Op.getOpcode();
2795 errs() << "Op.getOpcode() = " << Opc << "\n";
2885 unsigned Opc = (unsigned) N->getOpcode();
2891 errs() << "Op.getOpcode() = " << Opc << "\n";
2921 switch (N->getOpcode()) {
2926 if (Op0.getOpcode() == SPUISD::IndirectAddr
2927 || Op1.getOpcode() == SPUISD::IndirectAddr) {
2931 if (Op1.getOpcode() == SPUISD::IndirectAddr) {
2980 if (Op0.getOpcode() == SPUISD::VEC2PREFSLOT && NodeVT == Op0VT) {
2999 if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) {
3013 } else if (Op0.getOpcode
3049 switch (Op0.getOpcode()) {
3059 if (Op00.getOpcode() == SPUISD::VEC2PREFSLOT) {
3183 switch (Op.getOpcode()) {
3208 switch (Op.getOpcode()) {
