Lines Matching refs:VA
720 CCValAssign &VA = ArgLocs[i];
721 MVT RegVT = VA.getLocVT();
725 switch (VA.getLocInfo()) {
741 if (VA.isRegLoc()) {
742 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
745 assert(VA.isMemLoc());
753 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
754 unsigned StackLoc = VA.getLocMemOffset() + 4;
892 CCValAssign &VA = ArgLocs[i];
895 if (VA.isRegLoc()) {
896 MVT RegVT = VA.getLocVT();
897 ArgRegEnd = VA.getLocReg();
916 if (VA.getLocInfo() != CCValAssign::Full) {
918 if (VA.getLocInfo() == CCValAssign::SExt)
920 else if (VA.getLocInfo() == CCValAssign::ZExt)
924 DAG.getValueType(VA.getValVT()));
925 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
929 } else { // VA.isRegLoc()
931 assert(VA.isMemLoc());
944 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
945 unsigned StackLoc = VA.getLocMemOffset() + 4;
952 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1035 CCValAssign &VA = RVLocs[i];
1036 assert(VA.isRegLoc() && "Can only return in registers!");
1038 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
