Lines Matching full:pseudo
29 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
30 "# SelectF32 PSEUDO",
33 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
34 "# SelectF64 PSEUDO",
44 def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
47 def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
53 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
56 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
62 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
65 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
68 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
71 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
76 def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
79 def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
82 def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
85 def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
89 def FCOPYSIGN32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
92 def FCOPYSIGN64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
101 def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
105 def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
110 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
114 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
119 def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
123 def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
132 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
136 def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
142 def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
146 def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
151 def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
155 def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
160 def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
164 def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
171 def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
174 def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
179 def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
182 def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
186 def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
190 def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
196 def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
200 def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
206 def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
210 def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
216 def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
220 def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
226 def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
229 def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
233 def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
236 def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
242 def FSQRT32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
245 def FSQRT64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
249 def FSQRT32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
252 def FSQRT64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
256 def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
260 def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
263 def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
268 def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
272 def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
277 def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
281 def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
286 def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
290 def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
295 def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
299 def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
305 def FBCONVG64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
308 def FBCONVF64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
317 def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
320 def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
324 def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr12:$src2),
328 def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr12:$src2),
