Lines Matching full:x86
1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
53 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
161 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
162 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
165 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
167 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
212 FixupKind == MCFixupKind(X86::reloc_signed_4byte)) &&
216 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
223 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
224 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
245 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
246 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
247 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
248 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
252 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
257 unsigned FixupKind = X86::reloc_riprel_4byte;
262 if (MI.getOpcode() == X86::MOV64rm)
263 FixupKind = X86::reloc_riprel_4byte_movq_load;
294 if (BaseReg == 0) { // [disp32] in X86-32 mode
318 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
324 assert(IndexReg.getReg() != X86::ESP &&
325 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
379 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
493 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
507 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
509 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
512 CurOp = X86::AddrNumOperands;
535 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
538 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
542 VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1);
555 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
558 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
631 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
633 /// size, and 3) use of X86-64 extended registers.
694 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
735 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
738 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
739 case X86::SS: EmitByte(0x36, CurByte, OS); break;
740 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
741 case X86::ES: EmitByte(0x26, CurByte, OS); break;
742 case X86::FS: EmitByte(0x64, CurByte, OS); break;
743 case X86::GS: EmitByte(0x65, CurByte, OS); break;
937 SrcRegNum = CurOp + X86::AddrNumOperands;
963 int AddrOperands = X86::AddrNumOperands;
1000 CurOp += X86::AddrNumOperands;
1067 if (MI.getOpcode() == X86::ADD64ri32 ||
1068 MI.getOpcode() == X86::MOV64ri32 ||
1069 MI.getOpcode() == X86::MOV64mi32 ||
1070 MI.getOpcode() == X86::PUSH64i32)
1071 FixupKind = X86::reloc_signed_4byte;
