Lines Matching refs:Opcode
383 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
392 // VEX_R: opcode externsion equivalent to REX.R in
414 // VEX_W: opcode specific (use like REX.W, or used for
415 // opcode extension, or ignored, depending on the opcode byte)
421 // 0b00001: implied 0F leading opcode
422 opcode bytes
423 // 0b00011: implied 0F 3A leading opcode bytes
439 // VEX_PP: opcode extension providing equivalent
449 // Encode the operand size opcode prefix as needed.
603 // Emit segment override opcode prefix as needed.
606 // VEX opcode prefix can have 2 or 3 bytes
725 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
756 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
765 // Emit the lock opcode prefix as needed.
769 // Emit segment override opcode prefix as needed.
772 // Emit the repeat opcode prefix as needed.
776 // Emit the address size opcode prefix as needed.
781 // Emit the operand size opcode prefix as needed.
790 case X86II::TB: // Two-byte opcode prefix
830 // 0x0F escape code must be emitted just before the opcode.
856 unsigned Opcode = MI.getOpcode();
857 const MCInstrDesc &Desc = MCII.get(Opcode);
885 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
