Lines Matching full:x86
1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
62 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
164 // We only handle legal types. For example, on x86-32 the instruction
165 // selector contains all of the 64-bit instructions from x86-64,
185 Opc = X86::MOV8rm;
186 RC = X86::GR8RegisterClass;
189 Opc = X86::MOV16rm;
190 RC = X86::GR16RegisterClass;
193 Opc = X86::MOV32rm;
194 RC = X86::GR32RegisterClass;
197 // Must be in x86-64 mode.
198 Opc = X86::MOV64rm;
199 RC = X86::GR64RegisterClass;
203 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
204 RC = X86::FR32RegisterClass;
206 Opc = X86::LD_Fp32m;
207 RC = X86::RFP32RegisterClass;
212 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
213 RC = X86::FR64RegisterClass;
215 Opc = X86::LD_Fp64m;
216 RC = X86::RFP64RegisterClass;
243 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
245 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
249 case MVT::i8: Opc = X86::MOV8mr; break;
250 case MVT::i16: Opc = X86::MOV16mr; break;
251 case MVT::i32: Opc = X86::MOV32mr; break;
252 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
255 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
259 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
262 Opc = X86::MOVAPSmr;
265 Opc = X86::MOVAPDmr;
271 Opc = X86::MOVDQAmr;
293 case MVT::i8: Opc = X86::MOV8mi; break;
294 case MVT::i16: Opc = X86::MOV16mi; break;
295 case MVT::i32: Opc = X86::MOV32mi; break;
299 Opc = X86::MOV64mi32;
524 AM.Base.Reg = X86::RIP;
549 Opc = X86::MOV64rm;
550 RC = X86::GR64RegisterClass;
553 StubAM.Base.Reg = X86::RIP;
555 Opc = X86::MOV32rm;
556 RC = X86::GR32RegisterClass;
656 AM.Base.Reg = X86::RIP;
769 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
783 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
811 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
845 case MVT::i8: return X86::CMP8rr;
846 case MVT::i16: return X86::CMP16rr;
847 case MVT::i32: return X86::CMP32rr;
848 case MVT::i64: return X86::CMP64rr;
850 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
852 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
863 case MVT::i8: return X86::CMP8ri;
864 case MVT::i16: return X86::CMP16ri;
865 case MVT::i32: return X86::CMP32ri;
870 return X86::CMP64ri32;
915 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
923 unsigned EReg = createResultReg(&X86::GR8RegClass);
924 unsigned NPReg = createResultReg(&X86::GR8RegClass);
925 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
927 TII.get(X86::SETNPr), NPReg);
929 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
937 unsigned NEReg = createResultReg(&X86::GR8RegClass);
938 unsigned PReg = createResultReg(&X86::GR8RegClass);
939 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
940 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
946 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
947 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
948 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
949 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
950 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
951 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
952 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
953 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
954 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
955 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
956 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
957 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
959 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
960 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
961 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
962 X86::SETAEr; break;
963 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
964 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
965 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
966 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
967 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
968 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
1038 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
1045 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1046 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1047 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1048 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
1049 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
1050 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1051 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
1052 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
1053 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1054 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
1055 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
1056 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1057 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1059 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1060 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1061 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1062 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1063 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1064 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1065 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
1066 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
1067 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
1068 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
1085 // X86 requires a second branch to handle UNE (and OEQ,
1087 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1104 case MVT::i8: TestOpc = X86::TEST8ri; break;
1105 case MVT::i16: TestOpc = X86::TEST16ri; break;
1106 case MVT::i32: TestOpc = X86::TEST32ri; break;
1107 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1115 unsigned JmpOpc = X86::JNE_4;
1118 JmpOpc = X86::JE_4;
1136 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1149 CReg = X86::CL;
1150 RC = &X86::GR8RegClass;
1152 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1153 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1154 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1158 CReg = X86::CX;
1159 RC = &X86::GR16RegClass;
1161 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1162 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1163 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1167 CReg = X86::ECX;
1168 RC = &X86::GR32RegClass;
1170 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1171 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1172 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1176 CReg = X86::RCX;
1177 RC = &X86::GR64RegClass;
1179 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1180 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1181 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1200 // The shift instruction uses X86::CL. If we defined a super-register
1201 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1202 if (CReg != X86::CL)
1204 TII.get(TargetOpcode::KILL), X86::CL)
1225 Opc = X86::CMOVE16rr;
1226 RC = &X86::GR16RegClass;
1228 Opc = X86::CMOVE32rr;
1229 RC = &X86::GR32RegClass;
1231 Opc = X86::CMOVE64rr;
1232 RC = &X86::GR64RegClass;
1244 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1261 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1263 TII.get(X86::CVTSS2SDrr), ResultReg)
1280 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1282 TII.get(X86::CVTSD2SSrr), ResultReg)
1315 // If we're on x86-32; we can't extract an i8 from a general register.
1318 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1328 X86::sub_8bit);
1452 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1480 OpC = X86::ADD32rr;
1482 OpC = X86::ADD64rr;
1492 unsigned Opc = X86::SETBr;
1494 Opc = X86::SETOr;
1540 // x86-32. Special handling for x86-64 is implemented.
1545 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
1618 // calling conventions on x86.
1776 X86::EBX).addReg(Base);
1782 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1783 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1786 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri),
1787 X86::AL).addImm(NumXMMRegs);
1796 CallOpc = X86::WINCALL64r;
1798 CallOpc = X86::CALL64r;
1800 CallOpc = X86::CALL32r;
1809 CallOpc = X86::WINCALL64pcrel32;
1811 CallOpc = X86::CALL64pcrel32;
1813 CallOpc = X86::CALLpcrel32;
1818 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1846 MIB.addReg(X86::EBX);
1849 MIB.addReg(X86::AL);
1900 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1901 RVLocs[i].getLocReg() == X86::ST1)) {
1904 CopyReg = createResultReg(X86::RFP80RegisterClass);
1906 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
1919 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1925 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
2001 Opc = X86::MOV8rm;
2002 RC = X86::GR8RegisterClass;
2005 Opc = X86::MOV16rm;
2006 RC = X86::GR16RegisterClass;
2009 Opc = X86::MOV32rm;
2010 RC = X86::GR32RegisterClass;
2013 // Must be in x86-64 mode.
2014 Opc = X86::MOV64rm;
2015 RC = X86::GR64RegisterClass;
2019 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
2020 RC = X86::FR32RegisterClass;
2022 Opc = X86::LD_Fp32m;
2023 RC = X86::RFP32RegisterClass;
2028 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
2029 RC = X86::FR64RegisterClass;
2031 Opc = X86::LD_Fp64m;
2032 RC = X86::RFP64RegisterClass;
2050 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
2066 // x86-32 PIC requires a PIC base register for constant pools.
2077 PICBase = X86::RIP;
2104 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
2124 Opc = Subtarget->hasAVX() ? X86::VFsFLD0SS : X86::FsFLD0SS;
2125 RC = X86::FR32RegisterClass;
2127 Opc = X86::LD_Fp032;
2128 RC = X86::RFP32RegisterClass;
2133 Opc = Subtarget->hasAVX() ? X86::VFsFLD0SD : X86::FsFLD0SD;
2134 RC = X86::FR64RegisterClass;
2136 Opc = X86::LD_Fp064;
2137 RC = X86::RFP64RegisterClass;
2180 llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) {
