Lines Matching full:x86
1 //=======- X86FrameLowering.cpp - X86 Frame Information --------*- C++ -*-====//
10 // This file contains the X86 implementation of TargetFrameLowering class.
61 return X86::SUB64ri8;
62 return X86::SUB64ri32;
65 return X86::SUB32ri8;
66 return X86::SUB32ri;
73 return X86::ADD64ri8;
74 return X86::ADD64ri32;
77 return X86::ADD32ri8;
78 return X86::ADD32ri;
95 X86::EAX, X86::EDX, X86::ECX, 0
99 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
100 X86::R8, X86::R9, X86::R10, X86::R11, 0
106 case X86::RET:
107 case X86::RETI:
108 case X86::TCRETURNdi:
109 case X86::TCRETURNri:
110 case X86::TCRETURNmi:
111 case X86::TCRETURNdi64:
112 case X86::TCRETURNri64:
113 case X86::TCRETURNmi64:
114 case X86::EH_RETURN:
115 case X86::EH_RETURN64: {
159 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
163 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
164 : (Is64Bit ? X86::POP64r : X86::POP32r);
193 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
194 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
199 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
200 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
222 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
223 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
229 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
230 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
256 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
257 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
262 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
263 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
278 if (Reg == X86::EAX || Reg == X86::AX ||
279 Reg == X86::AH || Reg == X86::AL)
381 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
384 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
441 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
444 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
480 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
482 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
499 if (Opc == X86::PROLOG_LABEL) continue;
634 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
697 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
704 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
726 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
733 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
751 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
768 (MBBI->getOpcode() == X86::PUSH32r ||
769 MBBI->getOpcode() == X86::PUSH64r)) {
777 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
834 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
835 .addReg(X86::EAX, RegState::Kill)
842 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
848 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
854 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
857 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
868 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
869 X86::EAX),
881 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
928 case X86::RET:
929 case X86::RETI:
930 case X86::TCRETURNdi:
931 case X86::TCRETURNri:
932 case X86::TCRETURNmi:
933 case X86::TCRETURNdi64:
934 case X86::TCRETURNri64:
935 case X86::TCRETURNmi64:
936 case X86::EH_RETURN:
937 case X86::EH_RETURN64:
968 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
979 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1005 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1009 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1016 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1025 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1030 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1032 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1033 RetOpcode == X86::TCRETURNmi ||
1034 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1035 RetOpcode == X86::TCRETURNmi64) {
1036 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1060 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1062 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1063 ? X86::TAILJMPd : X86::TAILJMPd64));
1072 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1074 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1075 ? X86::TAILJMPm : X86::TAILJMPm64));
1078 } else if (RetOpcode == X86::TCRETURNri64) {
1079 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1082 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1092 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1156 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1159 if (!X86::GR64RegClass.contains(Reg) &&
1160 !X86::GR32RegClass.contains(Reg))
1174 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1179 if (X86::GR64RegClass.contains(Reg) ||
1180 X86::GR32RegClass.contains(Reg))
1207 if (X86::GR64RegClass.contains(Reg) ||
1208 X86::GR32RegClass.contains(Reg))
1217 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1220 if (!X86::GR64RegClass.contains(Reg) &&
1221 !X86::GR32RegClass.contains(Reg))
1286 return X86::R11;
1297 return X86::EAX;
1301 return X86::EDX;
1303 return X86::ECX;
1353 allocMBB->addLiveIn(X86::R10);
1354 restoreR10MBB->addLiveIn(X86::RAX);
1369 TlsReg = X86::FS;
1372 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1374 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1377 TlsReg = X86::GS;
1380 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1382 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1388 BuildMI(checkMBB, DL, TII.get(X86::JG_4)).addMBB(&prologueMBB);
1397 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1399 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1401 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1403 MF.getRegInfo().setPhysRegUsed(X86::R10);
1404 MF.getRegInfo().setPhysRegUsed(X86::R11);
1407 BuildMI(allocMBB, DL, TII.get(X86::SUB32ri), X86::ESP).addReg(X86::ESP)
1409 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1411 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1417 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1420 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1426 BuildMI(allocMBB, DL, TII.get(X86::ADD32ri), X86::ESP).addReg(X86::ESP)
1428 BuildMI(allocMBB, DL, TII.get(X86::RET));
1431 BuildMI(restoreR10MBB, DL, TII.get(X86::MOV64rr), X86::R10)
1432 .addReg(X86::RAX);
