Lines Matching refs:MIB
1355 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1363 MIB.addReg(0).addImm(1 << ShAmt)
1369 addRegOffset(MIB, leaInReg, true, 1);
1373 addRegOffset(MIB, leaInReg, true, -1);
1379 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1390 addRegReg(MIB, leaInReg, true, leaInReg, false);
1395 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1397 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1400 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1408 MachineInstr *NewMI = MIB;
2356 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2358 MIB.addOperand(Addr[i]);
2359 MIB.addReg(SrcReg, getKillRegState(isKill));
2360 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2361 NewMIs.push_back(MIB);
2390 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2392 MIB.addOperand(Addr[i]);
2393 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2394 NewMIs.push_back(MIB);
2439 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2440 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2441 return &*MIB;
2451 MachineInstrBuilder MIB(NewMI);
2454 MIB.addOperand(MOs[i]);
2456 addOffset(MIB, 0);
2462 MIB.addOperand(MO);
2466 MIB.addOperand(MO);
2468 return MIB;
2477 MachineInstrBuilder MIB(NewMI);
2485 MIB.addOperand(MOs[i]);
2487 addOffset(MIB, 0);
2489 MIB.addOperand(MO);
2492 return MIB;
2499 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2503 MIB.addOperand(MOs[i]);
2505 addOffset(MIB, 0);
2506 return MIB.addImm(0);
2944 MachineInstrBuilder MIB(DataMI);
2947 MIB.addReg(Reg, RegState::Define);
2949 MIB.addOperand(BeforeOps[i]);
2951 MIB.addReg(Reg);
2953 MIB.addOperand(AfterOps[i]);
2956 MIB.addReg(MO.getReg(),
