Lines Matching refs:RC
1600 TargetRegisterClass *RC;
1603 RC = X86::GR64_NOSPRegisterClass;
1606 RC = X86::GR32_NOSPRegisterClass;
1615 !MF.getRegInfo().constrainRegClass(Src2, RC))
2246 const TargetRegisterClass *RC,
2251 switch (RC->getSize()) {
2255 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2259 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2263 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2266 if (X86::GR32RegClass.hasSubClassEq(RC))
2268 if (X86::FR32RegClass.hasSubClassEq(RC))
2272 if (X86::RFP32RegClass.hasSubClassEq(RC))
2276 if (X86::GR64RegClass.hasSubClassEq(RC))
2278 if (X86::FR64RegClass.hasSubClassEq(RC))
2282 if (X86::VR64RegClass.hasSubClassEq(RC))
2284 if (X86::RFP64RegClass.hasSubClassEq(RC))
2288 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2291 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2303 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2313 const TargetRegisterClass *RC,
2316 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2321 const TargetRegisterClass *RC,
2324 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2330 const TargetRegisterClass *RC,
2333 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2335 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2338 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2347 const TargetRegisterClass *RC,
2351 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2354 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2368 const TargetRegisterClass *RC,
2371 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2374 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2381 const TargetRegisterClass *RC,
2385 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2388 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2901 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2903 RC == &X86::VR128RegClass &&
2931 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3022 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3045 EVT VT = *RC->vt_begin();
3051 RC == &X86::VR128RegClass &&
3055 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3058 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3095 RC == &X86::VR128RegClass &&
3099 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3299 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3302 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3303 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
