Lines Matching refs:getOpcode
923 switch (MI.getOpcode()) {
946 switch (MI.getOpcode()) {
1050 if (isFrameLoadOpcode(MI->getOpcode()))
1058 if (isFrameLoadOpcode(MI->getOpcode())) {
1071 if (isFrameStoreOpcode(MI->getOpcode()))
1080 if (isFrameStoreOpcode(MI->getOpcode())) {
1098 if (DefMI->getOpcode() != X86::MOVPC32r)
1109 switch (MI->getOpcode()) {
1155 if (DefMI->getOpcode() != X86::MOVPC32r)
1276 unsigned Opc = Orig->getOpcode();
1456 unsigned MIOpc = MI->getOpcode();
1697 switch (MI->getOpcode()) {
1706 switch (MI->getOpcode()) {
1774 switch (MI->getOpcode()) {
1943 if (I->getOpcode() == X86::JMP_4) {
1973 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2070 if (I->getOpcode() != X86::JMP_4 &&
2071 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2421 switch (MI->getOpcode()) {
2522 if (MI->getOpcode() == X86::ADD32ri &&
2537 if (MI->getOpcode() == X86::MOV64r0)
2539 else if (MI->getOpcode() == X86::MOV32r0)
2541 else if (MI->getOpcode() == X86::MOV16r0)
2543 else if (MI->getOpcode() == X86::MOV8r0)
2559 OpcodeTablePtr->find(MI->getOpcode());
2665 hasPartialRegUpdate(MI->getOpcode()))
2674 switch (MI->getOpcode()) {
2706 hasPartialRegUpdate(MI->getOpcode()))
2714 switch (LoadMI->getOpcode()) {
2737 switch (MI->getOpcode()) {
2756 switch (LoadMI->getOpcode()) {
2790 unsigned Opc = LoadMI->getOpcode();
2831 switch (MI->getOpcode()) {
2851 unsigned Opc = MI->getOpcode();
2886 MemOp2RegOpTable.find(MI->getOpcode());
2965 switch (DataMI->getOpcode()) {
2977 switch (DataMI->getOpcode()) {
3386 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3393 const unsigned *table = lookup(MI->getOpcode(), dom);
3462 return isHighLatencyDef(DefMI->getOpcode());
