Lines Matching full:x86
1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
10 // This file describes the X86 Register file, defining the registers themselves,
19 let Namespace = "X86" in {
38 // variations by target as well. Currently the first entry is for X86-64,
39 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
40 // and debug information on X86-32/Darwin)
49 // X86-64 only, requires REX.
65 // High registers. On x86-64, these cannot be used in any instruction
87 // X86-64 only, requires REX.
110 // X86-64 only, requires REX
122 // 64-bit registers, X86-64 only
177 // X86-64 only
278 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
288 def GR8 : RegisterClass<"X86", [i8], 8,
297 def GR16 : RegisterClass<"X86", [i16], 16,
303 def GR32 : RegisterClass<"X86", [i32], 32,
312 def GR64 : RegisterClass<"X86", [i64], 64,
323 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
326 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
329 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
333 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
334 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
337 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
338 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
339 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)> {
342 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)> {
347 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)> {
353 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)> {
356 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
363 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
367 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
375 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
380 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
386 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
396 def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)> {
401 def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)> {
406 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)> {
414 def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
421 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
429 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)> {
436 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
438 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
447 def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>;
448 def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;
449 def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;
454 def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {
459 def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;
460 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
465 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
471 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
