Lines Matching refs:DAG
1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===//
158 // We have target-specific dag combine patterns for the following nodes:
166 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
172 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
173 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
174 case ISD::LOAD: return LowerLOAD(Op, DAG);
175 case ISD::STORE: return LowerSTORE(Op, DAG);
176 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
177 case ISD::VAARG: return LowerVAARG(Op, DAG);
178 case ISD::VASTART: return LowerVASTART(Op, DAG);
179 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
180 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
183 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
184 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
185 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
186 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
197 SelectionDAG &DAG) const {
204 Results.push_back(ExpandADDSUB(N, DAG));
214 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
217 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
219 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
225 SelectionDAG &DAG) const
230 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
240 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
242 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
246 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
249 SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), MVT::i32);
250 return getGlobalAddressWrapper(GA, GV, DAG);
253 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
254 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
255 DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
264 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
270 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
289 SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
292 SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
293 DAG.getConstant(Size, MVT::i32));
294 return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
298 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
303 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
305 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
309 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
317 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
320 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
323 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
331 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
339 MachineFunction &MF = DAG.getMachineFunction();
341 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
345 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
348 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
349 DAG.getConstant(1, MVT::i32));
350 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
393 LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
402 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
419 return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
429 SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32);
430 SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32);
431 SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
432 SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
434 SDValue LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowOffset);
435 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset);
437 SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
439 SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
441 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
442 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
443 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
444 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
447 return DAG.getMergeValues(Ops, 2, DL);
451 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
454 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
455 DAG.getConstant(2, MVT::i32));
456 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
461 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
462 DAG.getConstant(16, MVT::i32));
463 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
464 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
467 return DAG.getMergeValues(Ops, 2, DL);
471 Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
483 DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
484 Args, DAG, DL);
489 return DAG.getMergeValues(Ops, 2, DL);
493 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
502 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
514 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
515 DAG.getConstant(16, MVT::i32));
516 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
520 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
521 DAG.getConstant(2, MVT::i32));
522 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
526 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
530 Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
542 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false,
545 DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
546 Args, DAG, dl);
552 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
559 SDValue Zero = DAG.getConstant(0, MVT::i32);
560 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
561 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
565 return DAG.getMergeValues(Ops, 2, dl);
569 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
576 SDValue Zero = DAG.getConstant(0, MVT::i32);
577 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
578 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
582 return DAG.getMergeValues(Ops, 2, dl);
645 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
660 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
661 Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
662 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
663 Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
664 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
665 Other, DAG.getConstant(0, MVT::i32));
666 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
667 Other, DAG.getConstant(1, MVT::i32));
669 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
670 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
671 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
672 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
674 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
675 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
678 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
682 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
683 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
686 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
689 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
690 Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
691 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
692 Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
693 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
694 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
697 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
698 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
699 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
700 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
701 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
705 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
712 SDValue Result = TryExpandADDWithMul(N, DAG);
720 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
721 N->getOperand(0), DAG.getConstant(0, MVT::i32));
722 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
723 N->getOperand(0), DAG.getConstant(1, MVT::i32));
724 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
725 N->getOperand(1), DAG.getConstant(0, MVT::i32));
726 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
727 N->getOperand(1), DAG.getConstant(1, MVT::i32));
732 SDValue Zero = DAG.getConstant(0, MVT::i32);
733 SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
737 SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
741 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
745 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
753 SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
757 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
758 DAG.getConstant(VT.getSizeInBits(),
761 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1),
764 return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
769 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
774 MachineFunction &MF = DAG.getMachineFunction();
776 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
777 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
782 SelectionDAG &DAG) const {
788 MachineFunction &MF = DAG.getMachineFunction();
790 return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
795 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
800 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
824 OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
828 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
829 DAG.getConstant(4, MVT::i32));
830 OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
834 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
835 DAG.getConstant(8, MVT::i32));
836 OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
840 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
841 DAG.getConstant(12, MVT::i32));
842 OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
846 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
847 DAG
848 OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
852 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5);
873 DebugLoc dl, SelectionDAG &DAG,
886 Outs, OutVals, Ins, dl, DAG, InVals);
901 DebugLoc dl, SelectionDAG &DAG,
906 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
907 getTargetMachine(), ArgLocs, *DAG.getContext());
918 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
934 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
937 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
940 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
953 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
955 DAG.getConstant(Offset/4, MVT::i32)));
962 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
971 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
980 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
982 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
988 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
996 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1002 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
1006 Chain = DAG.getCALLSEQ_END(Chain,
1007 DAG.getConstant(NumBytes, getPointerTy(), true),
1008 DAG.getConstant(0, getPointerTy(), true),
1015 Ins, dl, DAG, InVals);
1024 DebugLoc dl, SelectionDAG &DAG,
1029 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1030 getTargetMachine(), RVLocs, *DAG.getContext());
1036 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1056 SelectionDAG &DAG,
1066 Ins, dl, DAG, InVals);
1081 SelectionDAG &DAG,
1083 MachineFunction &MF = DAG.getMachineFunction();
1089 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1090 getTargetMachine(), ArgLocs, *DAG.getContext());
1118 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1137 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1138 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1164 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1169 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1171 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1176 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1208 DebugLoc dl, SelectionDAG &DAG) const {
1215 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1216 getTargetMachine(), RVLocs, *DAG.getContext());
1223 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1226 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1236 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1246 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1247 Chain, DAG.getConstant(0, MVT::i32), Flag);
1249 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1250 Chain, DAG.getConstant(0, MVT::i32));
1326 SelectionDAG &DAG = DCI.DAG;
1340 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1344 SDValue Carry = DAG.getConstant(0, VT);
1345 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1346 DAG.getConstant(1, VT));
1348 return DAG.getMergeValues(Ops, 2, dl);
1357 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1359 SDValue Carry = DAG.getConstant(0, VT);
1360 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1362 return DAG.getMergeValues(Ops, 2, dl);
1380 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1383 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1384 DAG.getConstant(0, VT), N2);
1386 return DAG.getMergeValues(Ops, 2, dl);
1396 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1398 SDValue Borrow = DAG.getConstant(0, VT);
1399 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1401 return DAG.getMergeValues(Ops, 2, dl);
1418 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1425 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1427 return DAG.getMergeValues(Ops, 2, dl);
1430 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1442 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1443 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1455 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1456 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1457 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1458 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1459 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1460 Mul0, DAG.getConstant(0, MVT::i32));
1461 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1462 Mul1, DAG.getConstant(0, MVT::i32));
1463 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1464 Addend0, DAG.getConstant(0, MVT::i32));
1465 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1466 Addend1, DAG.getConstant(0, MVT::i32));
1467 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1468 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1471 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1490 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1501 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1503 DAG.getConstant(StoreBits/8, MVT::i32),
1518 const SelectionDAG &DAG,
