Lines Matching full:i64
105 define <1 x i64> @v_movi64() nounwind {
107 ;CHECK: vmov.i64 d{{.*}}, #0xFF0000FF0000FFFF
108 ret <1 x i64> < i64 18374687574888349695 >
165 define <2 x i64> @v_movQi64() nounwind {
167 ;CHECK: vmov.i64 q{{.*}}, #0xFF0000FF0000FFFF
168 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
207 define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
211 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
212 ret <2 x i64> %tmp2
231 define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
235 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
236 ret <2 x i64> %tmp2
255 define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
257 ;CHECK: vmovn.i64
258 %tmp1 = load <2 x i64>* %A
259 %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
279 define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
282 %tmp1 = load <2 x i64>* %A
283 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
303 define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
306 %tmp1 = load <2 x i64>* %A
307 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
327 define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
330 %tmp1 = load <2 x i64>* %A
331 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
337 declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
341 declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
345 declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
