Lines Matching full:i64
19 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
22 %tmp1 = load <2 x i64>* %A
23 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
43 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
46 %tmp1 = load <2 x i64>* %A
47 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
67 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
70 %tmp1 = load <2 x i64>* %A
71 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
77 declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
81 declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
85 declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
103 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
106 %tmp1 = load <2 x i64>* %A
107 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
127 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
130 %tmp1 = load <2 x i64>* %A
131 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
151 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
154 %tmp1 = load <2 x i64>* %A
155 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
161 declare <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
165 declare <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
169 declare <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
