Lines Matching refs:RC
339 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
340 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
341 ArrayRef<Record*> Order = RC.getOrder();
344 std::string Name = RC.getName();
372 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
373 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
374 OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
375 << '\"' << RC.getName() << "\", "
376 << RC.SpillSize/8 << ", "
377 << RC.SpillAlignment/8 << ", "
378 << RC.CopyCost << ", "
379 << RC.Allocatable << ", "
380 << RC.getName() << ", " << RC.getName() << " + "
381 << RC.getOrder().size() << ", "
382 << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
455 const CodeGenRegisterClass &RC = *RegisterClasses[i];
456 const std::string &Name = RC.getName();
461 if (!RC.AltOrderSelect.empty())
502 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
503 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
504 ArrayRef<Record*> Order = RC.getOrder();
506 if (RC.Allocatable)
513 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
514 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
517 std::string Name = RC.getName() + "VTs";
524 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
525 OS << getEnumName(RC.VTs[i]) << ", ";
547 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
548 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
550 i = RC.SubRegClasses.begin(),
551 e = RC.SubRegClasses.end(); i != e; ++i) {
555 SuperRegClassMap[RC2->EnumValue].insert(rc);
560 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
561 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
564 std::string Name = RC.getName();
573 SuperRegClassMap.find(rc);
591 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
592 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
595 std::string Name = RC.getName();
598 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
603 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
604 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
605 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
612 << RC.getName() << "Superclasses[] = {\n";
620 const CodeGenRegisterClass &RC = *RegisterClasses[i];
621 OS << RC.getName() << "Class::" << RC.getName()
624 << RC.getName() + "RegClassID" << "], "
625 << RC.getName() + "VTs" << ", "
626 << RC.getName() + "SubclassMask" << ", ";
627 if (RC.getSuperClasses().empty())
630 OS << RC.getName() + "Superclasses, ";
631 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
634 if (!RC.AltOrderSelect.empty()) {
635 OS << "\nstatic inline unsigned " << RC.getName()
637 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
638 << RC.getName() << "Class::"
640 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
641 ArrayRef<Record*> Elems = RC.getOrder(oi);
648 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];"
651 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
653 OS << ")\n };\n const unsigned Select = " << RC.getName()
654 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
784 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
788 << " return RC;\n";
800 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
801 OS << " {\t// " << RC.getName() << "\n";
804 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
812 OS << " };\n assert(RC && \"Missing regclass\");\n"
813 << " if (!Idx) return RC;\n --Idx;\n"
815 << " unsigned TV = Table[RC->getID()][Idx];\n"
