Lines Matching full:x40
28 0x40 pdp_miss Number of DTLB cache load misses where the high part of the linear to physical address translation was missed
56 0x40 sse_single_precision Counts number of SSE* FP single precision uops executed
65 0x40 shuffle_move Counts number of 128 bit SIMD integer shuffle and move operations
90 0x40 prefetch_hit Counts L2 prefetch hits for both code and data
103 0x40 e_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state
116 0x40 e_state Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the E (exclusive) state
159 0x40 pdp_miss Number of DTLB misses where the high part of the linear to physical address translation was missed
202 0x40 pdp_miss Number of ITLB misses where the high part of the linear to physical address translation was missed
219 0x40 taken Counts taken near branches executed, but not necessarily retired
230 0x40 taken Counts executed mispredicted near branches that are taken, but not necessarily retired
239 0x40 mxcsr Stalls due to the MXCSR register rename occurring to close to a previous MXCSR rename
248 0x40 l1d_writeback Counts number of L1D writebacks to the uncore
257 0x40 port015 Counts number of Uops executed that where issued on port 0, 1, or 5
302 0x40 hit_lfb Counts number of retired loads that miss the L1D and the address is located in an allocated line fill buffer and will soon be committed to cache
334 0x40 wb Counts L2 writeback operations to the LLC
370 0x40 shuffle_move Counts number of SID integer 64 bit shift or move operations
