Lines Matching refs:enabled
42 unsigned enabled:1;
52 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
53 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
54 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
82 int enabled;
102 /* Update interrupt status after enabled or pending bits have been changed. */
115 if (!s->enabled || !s->cpu_enabled[cpu]) {
256 return s->enabled;
388 s->enabled = (value & 1);
389 DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
407 DPRINTF("Enabled IRQ %d\n", irq + i);
409 /* If a raised level triggered IRQ enabled then mark
640 /* The NVIC is always enabled. */
641 s->enabled = 1;
643 s->enabled = 0;
653 qemu_put_be32(f, s->enabled);
672 qemu_put_byte(f, s->irq_state[i].enabled);
690 s->enabled = qemu_get_be32(f);
709 s->irq_state[i].enabled = qemu_get_byte(f);
