Lines Matching refs:opcode
24 /* ppc.h -- Header file for PowerPC opcode table
45 /* The opcode table is an array of struct powerpc_opcode. */
49 /* The opcode name. */
52 /* The opcode itself. Those bits which will be filled in with
54 unsigned long opcode;
56 /* The opcode mask. This is used by the disassembler. This is a
58 opcode field, and zeroes indicating those bits which need not
62 /* One bit flags for the opcode. These are used to indicate which
73 /* The table itself is sorted by major opcode number, and is otherwise
81 /* Opcode is defined for the PowerPC architecture. */
84 /* Opcode is defined for the POWER (RS/6000) architecture. */
87 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
90 /* Opcode is only defined on 32 bit architectures. */
93 /* Opcode is only defined on 64 bit architectures. */
96 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
101 /* Opcode is supported in both the Power and PowerPC architectures
105 /* Opcode is supported for any Power or PowerPC platform (this is
109 /* Opcode is supported as part of the 64-bit bridge. */
112 /* Opcode is supported by Altivec Vector Unit */
115 /* Opcode is supported by PowerPC 403 processor. */
118 /* Opcode is supported by PowerPC BookE processor. */
121 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
124 /* Opcode is supported by PowerPC 440 processor. */
127 /* Opcode is only supported by Power4 architecture. */
130 /* Opcode isn't supported by Power4 architecture. */
133 /* Opcode is only supported by POWERPC Classic architecture. */
136 /* Opcode is only supported by e500x2 Core. */
139 /* Opcode is supported by e500x2 Integer select APU. */
142 /* Opcode is an e500 SPE floating point instruction. */
145 /* Opcode is supported by branch locking APU. */
148 /* Opcode is supported by performance monitor APU. */
151 /* Opcode is supported by cache locking APU. */
154 /* Opcode is supported by machine check APU. */
157 /* Opcode is only supported by Power5 architecture. */
160 /* Opcode is supported by PowerPC e300 family. */
163 /* Opcode is only supported by Power6 architecture. */
166 /* Opcode is only supported by PowerPC Cell family. */
169 /* A macro to extract the major opcode from an instruction. */
288 and the number of operands remaining for the opcode, and decide
295 1, ignoring the next operand field for the opcode. This wretched
334 /* One bit flags for the opcode. These are used to indicate which
348 /* ppc-opc.c -- PowerPC opcode list
369 /* This file holds the PowerPC opcode table. The opcode table
665 description in opcode/ppc.h for what this means. */
1596 /* The main opcode. */
1600 /* The main opcode combined with a trap code in the TO field of a D
1606 /* The main opcode combined with a comparison size bit in the L field
1668 /* The main opcode mask with the RA field clear. */
1996 /* The opcode table.
1998 The format of the opcode table is:
2000 NAME OPCODE MASK FLAGS { OPERANDS }
2003 OPCODE is the instruction opcode.
2004 MASK is the opcode mask; this is used to tell the disassembler
2005 which bits in the actual opcode must match OPCODE.
2012 sorted by major opcode. */
5258 const struct powerpc_opcode *opcode;
5277 /* Get the major opcode of the instruction. */
5280 /* Find the first match in the opcode table. We could speed this up
5281 a bit by doing a binary search on the major opcode. */
5284 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
5294 table_op = PPC_OP (opcode->opcode);
5300 if ((insn & opcode->mask) != opcode->opcode
5301 || (opcode->flags & dialect) == 0)
5308 for (opindex = opcode->operands; *opindex != 0; opindex++)
5318 if (opcode->operands[0] != 0)
5319 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
5321 (*info->fprintf_func) (info->stream, "%s", opcode->name);
5327 for (opindex = opcode->operands; *opindex != 0; opindex++)
