Lines Matching refs:instr
59 void Stop(Instruction* instr);
63 static const Instr kBreakpointInstr =
65 static const Instr kNopInstr = (al | (13*B21));
109 void ArmDebugger::Stop(Instruction* instr) {
111 uint32_t code = instr->SvcValue() & kStopCodeMask;
129 instr->SetInstructionBits(kNopInstr);
141 void ArmDebugger::Stop(Instruction* instr) {
143 uint32_t code = instr->SvcValue() & kStopCodeMask;
700 Instruction* instr) {
701 intptr_t address = reinterpret_cast<intptr_t>(instr);
711 CHECK(memcmp(reinterpret_cast<void*>(instr),
1056 int Simulator::ReadW(int32_t addr, Instruction* instr) {
1067 reinterpret_cast<intptr_t>(instr));
1074 void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
1087 reinterpret_cast<intptr_t>(instr));
1093 uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
1104 reinterpret_cast<intptr_t>(instr));
1111 int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
1127 void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
1140 reinterpret_cast<intptr_t>(instr));
1146 void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
1159 reinterpret_cast<intptr_t>(instr));
1233 void Simulator::Format(Instruction* instr, const char* format) {
1235 reinterpret_cast<intptr_t>(instr), format);
1242 bool Simulator::ConditionallyExecute(Instruction* instr) {
1243 switch (instr->ConditionField()) {
1360 int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
1361 ShiftOp shift = instr->ShiftField();
1362 int shift_amount = instr->ShiftAmountValue();
1363 int32_t result = get_register(instr->RmValue());
1364 if (instr->Bit(4) == 0) {
1427 int rs = instr->RsValue();
1504 int32_t Simulator::GetImm(Instruction* instr, bool* carry_out) {
1505 int rotate = instr->RotateValue() * 2;
1506 int immed8 = instr->Immed8Value();
1525 void Simulator::ProcessPUW(Instruction* instr,
1530 int rn = instr
1532 switch (instr->PUField()) {
1560 if (instr->HasW()) {
1566 void Simulator::HandleRList(Instruction* instr, bool load) {
1567 int rlist = instr->RlistValue();
1572 ProcessPUW(instr, num_regs, kPointerSize, &start_address, &end_address);
1593 void Simulator::HandleVList(Instruction* instr) {
1595 (instr->SzValue() == 0) ? kSinglePrecision : kDoublePrecision;
1598 bool load = (instr->VLValue() == 0x1);
1602 vd = instr->VFPDRegValue(precision);
1604 num_regs = instr->Immed8Value();
1606 num_regs = instr->Immed8Value() / 2;
1611 ProcessPUW(instr, num_regs, operand_size, &start_address, &end_address);
1618 reg, ReadW(reinterpret_cast<int32_t>(address), instr));
1621 get_sinteger_from_s_register(reg), instr);
1627 2 * reg, ReadW(reinterpret_cast<int32_t>(address), instr));
1629 2 * reg + 1, ReadW(reinterpret_cast<int32_t>(address + 1), instr));
1632 get_sinteger_from_s_register(2 * reg), instr);
1634 get_sinteger_from_s_register(2 * reg + 1), instr);
1670 void Simulator::SoftwareInterrupt(Instruction* instr) {
1671 int svc = instr->SvcValue();
1679 Redirection* redirection = Redirection::FromSwiInstruction(instr);
1793 dbg.Stop(instr);
1808 bool Simulator::isStopInstruction(Instruction* instr) {
1809 return (instr->Bits(27, 24) == 0xF) && (instr->SvcValue() >= kStopCode);
1883 void Simulator::DecodeType01(Instruction* instr) {
1884 int type = instr->TypeValue();
1885 if ((type == 0) && instr->IsSpecialType0()) {
1887 if (instr->Bits(7, 4) == 9) {
1888 if (instr->Bit(24) == 0) {
1891 int rn = instr->RnValue();
1892 int rm = instr->RmValue();
1893 int rs = instr->RsValue();
1896 if (instr->Bit(23) == 0) {
1897 if (instr->Bit(21) == 0) {
1901 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
1905 if (instr->HasS()) {
1913 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
1925 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
1927 int rd_lo = instr->RdValue();
1930 if (instr->Bit(22) == 1) {
1946 if (instr->HasS()) {
1955 int rd = instr->RdValue();
1956 int rn = instr->RnValue();
1959 if (instr->Bit(22) == 0) {
1960 int rm = instr->RmValue();
1962 switch (instr->PUField()) {
1964 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
1965 ASSERT(!instr->HasW());
1972 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
1973 ASSERT(!instr->HasW());
1980 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
1983 if (instr->HasW()) {
1989 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
1992 if (instr->HasW()) {
2004 int32_t imm_val = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
2005 switch (instr->PUField()) {
2007 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
2008 ASSERT(!instr->HasW());
2015 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
2016 ASSERT(!instr->HasW());
2023 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
2026 if (instr->HasW()) {
2032 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
2035 if (instr->HasW()) {
2047 if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) {
2049 if (instr->HasH()) {
2059 } else if (instr->HasH()) {
2060 if (instr->HasSign()) {
2061 if (instr->HasL()) {
2062 int16_t val = ReadH(addr, instr);
2066 WriteH(addr, val, instr);
2069 if (instr->HasL()) {
2070 uint16_t val = ReadHU(addr, instr);
2074 WriteH(addr, val, instr);
2079 ASSERT(instr->HasSign());
2080 ASSERT(instr->HasL());
2086 } else if ((type == 0) && instr->IsMiscType0()) {
2087 if (instr->Bits(22, 21) == 1) {
2088 int rm = instr->RmValue();
2089 switch (instr->BitField(7, 4)) {
2108 } else if (instr->Bits(22, 21) == 3) {
2109 int rm = instr->RmValue();
2110 int rd = instr->RdValue();
2111 switch (instr->BitField(7, 4)) {
2130 PrintF("%08x\n", instr->InstructionBits());
2134 int rd = instr->RdValue();
2135 int rn = instr->RnValue();
2140 shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2142 ASSERT(instr->TypeValue() == 1);
2143 shifter_operand = GetImm(instr, &shifter_carry_out);
2147 switch (instr->OpcodeField()) {
2149 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
2150 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
2153 if (instr->HasS()) {
2161 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
2162 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
2165 if (instr->HasS()) {
2173 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
2174 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
2177 if (instr->HasS()) {
2186 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
2187 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
2190 if (instr->HasS()) {
2199 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
2200 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
2203 if (instr->HasS()) {
2212 Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
2213 Format(instr, "adc'cond's 'rd, 'rn, 'imm");
2218 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
2219 Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
2224 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
2225 Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
2230 if (instr->HasS()) {
2231 // Format(instr, "tst'cond 'rn, 'shift_rm");
2232 // Format(instr, "tst'cond 'rn, 'imm");
2237 // Format(instr, "movw'cond 'rd, 'imm").
2238 alu_out = instr->ImmedMovwMovtValue();
2245 if (instr->HasS()) {
2246 // Format(instr, "teq'cond 'rn, 'shift_rm");
2247 // Format(instr, "teq'cond 'rn, 'imm");
2260 if (instr->HasS()) {
2261 // Format(instr, "cmp'cond 'rn, 'shift_rm");
2262 // Format(instr, "cmp'cond 'rn, 'imm");
2268 // Format(instr, "movt'cond 'rd, 'imm").
2270 (instr->ImmedMovwMovtValue() << 16);
2277 if (instr->HasS()) {
2278 // Format(instr, "cmn'cond 'rn, 'shift_rm");
2279 // Format(instr, "cmn'cond 'rn, 'imm");
2293 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
2294 // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
2297 if (instr->HasS()) {
2305 // Format(instr, "mov'cond's 'rd, 'shift_rm");
2306 // Format(instr, "mov'cond's 'rd, 'imm");
2309 if (instr->HasS()) {
2317 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
2318 // Format(instr, "bic'cond's 'rd, 'rn, 'imm");
2321 if (instr->HasS()) {
2329 // Format(instr, "mvn'cond's 'rd, 'shift_rm");
2330 // Format(instr, "mvn'cond's 'rd, 'imm");
2333 if (instr->HasS()) {
2349 void Simulator::DecodeType2(Instruction* instr) {
2350 int rd = instr->RdValue();
2351 int rn = instr->RnValue();
2353 int32_t im_val = instr->Offset12Value();
2355 switch (instr->PUField()) {
2357 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
2358 ASSERT(!instr->HasW());
2365 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
2366 ASSERT(!instr->HasW());
2373 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
2376 if (instr->HasW()) {
2382 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
2385 if (instr->HasW()) {
2395 if (instr->HasB()) {
2396 if (instr->HasL()) {
2404 if (instr->HasL()) {
2405 set_register(rd, ReadW(addr, instr));
2407 WriteW(addr, get_register(rd), instr);
2413 void Simulator::DecodeType3(Instruction* instr) {
2414 int rd = instr->RdValue();
2415 int rn = instr->RnValue();
2418 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2420 switch (instr->PUField()) {
2422 ASSERT(!instr->HasW());
2423 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
2428 if (instr->HasW()) {
2429 ASSERT(instr->Bits(5, 4) == 0x1);
2431 if (instr->Bit(22) == 0x1) { // USAT.
2432 int32_t sat_pos = instr->Bits(20, 16);
2434 int32_t shift = instr->Bits(11, 7);
2435 int32_t shift_type = instr->Bit(6);
2436 int32_t rm_val = get_register(instr->RmValue());
2456 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
2462 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
2464 if (instr->HasW()) {
2470 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
2471 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
2472 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
2475 if (instr->Bit(22)) {
2478 static_cast<uint32_t>(get_register(instr->RmValue()));
2481 set_register(instr->RdValue(), extr_val);
2484 int32_t rm_val = get_register(instr->RmValue());
2487 set_register(instr->RdValue(), extr_val);
2493 } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
2494 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
2495 uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
2499 static_cast<uint32_t>(get_register(instr->RdValue()));
2503 if (instr->RmValue() != 15) {
2506 static_cast<uint32_t>(get_register(instr->RmValue()));
2510 set_register(instr->RdValue(), rd_val);
2516 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
2518 if (instr->HasW()) {
2529 if (instr->HasB()) {
2530 if (instr->HasL()) {
2538 if (instr->HasL()) {
2539 set_register(rd, ReadW(addr, instr));
2541 WriteW(addr, get_register(rd), instr);
2547 void Simulator::DecodeType4(Instruction* instr) {
2548 ASSERT(instr->Bit(22) == 0); // only allowed to be set in privileged mode
2549 if (instr->HasL()) {
2550 // Format(instr
2551 HandleRList(instr, true);
2553 // Format(instr, "stm'cond'pu 'rn'w, 'rlist");
2554 HandleRList(instr, false);
2559 void Simulator::DecodeType5(Instruction* instr) {
2560 // Format(instr, "b'l'cond 'target");
2561 int off = (instr->SImmed24Value() << 2);
2563 if (instr->HasLink()) {
2571 void Simulator::DecodeType6(Instruction* instr) {
2572 DecodeType6CoprocessorIns(instr);
2576 void Simulator::DecodeType7(Instruction* instr) {
2577 if (instr->Bit(24) == 1) {
2578 SoftwareInterrupt(instr);
2580 DecodeTypeVFP(instr);
2585 // void Simulator::DecodeTypeVFP(Instruction* instr)
2600 void Simulator::DecodeTypeVFP(Instruction* instr) {
2601 ASSERT((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
2602 ASSERT(instr->Bits(11, 9) == 0x5);
2605 int vm = instr->VFPMRegValue(kDoublePrecision);
2606 int vd = instr->VFPDRegValue(kDoublePrecision);
2607 int vn = instr->VFPNRegValue(kDoublePrecision);
2609 if (instr->Bit(4) == 0) {
2610 if (instr->Opc1Value() == 0x7) {
2612 if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
2614 if (instr->SzValue() == 0x1) {
2615 int m = instr->VFPMRegValue(kDoublePrecision);
2616 int d = instr->VFPDRegValue(kDoublePrecision);
2619 int m = instr->VFPMRegValue(kSinglePrecision);
2620 int d = instr->VFPDRegValue(kSinglePrecision);
2623 } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) {
2628 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) {
2633 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
2634 DecodeVCVTBetweenDoubleAndSingle(instr);
2635 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
2636 DecodeVCVTBetweenFloatingPointAndInteger(instr);
2637 } else if (((instr->Opc2Value() >> 1) == 0x6) &&
2638 (instr->Opc3Value() & 0x1)) {
2639 DecodeVCVTBetweenFloatingPointAndInteger(instr);
2640 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
2641 (instr->Opc3Value() & 0x1)) {
2642 DecodeVCMP(instr);
2643 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
2648 } else if (instr->Opc3Value() == 0x0) {
2650 if (instr->SzValue() == 0x1) {
2651 set_d_register_from_double(vd, instr->DoubleImmedVmov());
2658 } else if (instr->Opc1Value() == 0x3) {
2659 if (instr->SzValue() != 0x1) {
2663 if (instr->Opc3Value() & 0x1) {
2676 } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
2678 if (instr->SzValue() != 0x1) {
2686 } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
2688 if (instr->SzValue() != 0x1) {
2701 if ((instr->VCValue() == 0x0) &&
2702 (instr->VAValue() == 0x0)) {
2703 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
2704 } else if ((instr->VLValue() == 0x1) &&
2705 (instr->VCValue() == 0x0) &&
2706 (instr->VAValue() == 0x7) &&
2707 (instr->Bits(19, 16) == 0x1)) {
2709 uint32_t rt = instr->RtValue();
2726 } else if ((instr->VLValue() == 0x0) &&
2727 (instr->VCValue() == 0x0) &&
2728 (instr->VAValue() == 0x7) &&
2729 (instr->Bits(19, 16) == 0x1)) {
2731 uint32_t rt = instr->RtValue();
2756 Instruction* instr) {
2757 ASSERT((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
2758 (instr->VAValue() == 0x0));
2760 int t = instr->RtValue();
2761 int n = instr->VFPNRegValue(kSinglePrecision);
2762 bool to_arm_register = (instr->VLValue() == 0x1);
2774 void Simulator::DecodeVCMP(Instruction* instr) {
2775 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
2776 ASSERT(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
2777 (instr->Opc3Value() & 0x1));
2781 if (instr->SzValue() == 1) {
2785 int d = instr->VFPDRegValue(precision);
2787 if (instr->Opc2Value() == 0x4) {
2788 m = instr->VFPMRegValue(precision);
2794 if (instr->Opc2Value() == 0x4) {
2799 if (instr->Bit(7) == 1) {
2812 void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
2813 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
2814 ASSERT((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
2818 if (instr->SzValue() == 1) {
2823 int dst = instr->VFPDRegValue(dst_precision);
2824 int src = instr->VFPMRegValue(src_precision);
2890 void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
2891 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7) &&
2892 (instr->Bits(27, 23) == 0x1D));
2893 ASSERT(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
2894 (((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
2897 bool to_integer = (instr->Bit(18) == 1);
2899 VFPRegPrecision src_precision = (instr->SzValue() == 1) ? kDoublePrecision
2910 int dst = instr->VFPDRegValue(kSinglePrecision);
2911 int src = instr->VFPMRegValue(src_precision);
2915 VFPRoundingMode mode = (instr->Bit(7) != 1) ? FPSCR_rounding_mode_
2919 bool unsigned_integer = (instr->Bit(16) == 0);
2968 bool unsigned_integer = (instr->Bit(7) == 0);
2970 int dst = instr->VFPDRegValue(src_precision);
2971 int src = instr->VFPMRegValue(kSinglePrecision);
2994 // void Simulator::DecodeType6CoprocessorIns(Instruction* instr)
3000 void Simulator::DecodeType6CoprocessorIns(Instruction* instr) {
3001 ASSERT((instr->TypeValue() == 6));
3003 if (instr->CoprocessorValue() == 0xA) {
3004 switch (instr->OpcodeValue()) {
3009 int rn = instr->RnValue();
3010 int vd = instr->VFPDRegValue(kSinglePrecision);
3011 int offset = instr->Immed8Value();
3012 if (!instr->HasU()) {
3017 if (instr->HasL()) {
3019 set_s_register_from_sinteger(vd, ReadW(address, instr));
3022 WriteW(address, get_sinteger_from_s_register(vd), instr);
3033 HandleVList(instr);
3038 } else if (instr->CoprocessorValue() == 0xB) {
3039 switch (instr->OpcodeValue()) {
3042 if (instr->Bits(7, 4) != 0x1) {
3045 int rt = instr->RtValue();
3046 int rn = instr->RnValue();
3047 int vm = instr->VmValue();
3048 if (instr->HasL()) {
3065 int rn = instr->RnValue();
3066 int vd = instr->VdValue();
3067 int offset = instr->Immed8Value();
3068 if (!instr->HasU()) {
3072 if (instr->HasL()) {
3074 set_s_register_from_sinteger(2*vd, ReadW(address, instr));
3075 set_s_register_from_sinteger(2*vd + 1, ReadW(address + 4, instr));
3078 WriteW(address, get_sinteger_from_s_register(2*vd), instr);
3079 WriteW(address + 4, get_sinteger_from_s_register(2*vd + 1), instr);
3087 HandleVList(instr);
3099 void Simulator::InstructionDecode(Instruction* instr) {
3101 CheckICache(isolate_->simulator_i_cache(), instr);
3110 reinterpret_cast<byte*>(instr));
3111 PrintF(" 0x%08x %s\n", reinterpret_cast<intptr_t>(instr), buffer.start());
3113 if (instr->ConditionField() == kSpecialCondition) {
3115 } else if (ConditionallyExecute(instr)) {
3116 switch (instr->TypeValue()) {
3119 DecodeType01(instr);
3123 DecodeType2(instr);
3127 DecodeType3(instr);
3131 DecodeType4(instr);
3135 DecodeType5(instr);
3139 DecodeType6(instr);
3143 DecodeType7(instr);
3153 } else if (instr->IsStop()) {
3157 set_register(pc, reinterpret_cast<int32_t>(instr)
3172 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
3174 InstructionDecode(instr);
3181 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
3187 InstructionDecode(instr);
