Lines Matching full:mmx
5359 /*--- MMX INSTRUCTIONS ---*/
5363 /* Effect of MMX insns on x87 FPU state (table 11-2 of
5366 Read from, or write to MMX register (viz, any insn except EMMS):
5413 /* Helper for non-shift MMX insns. Note this is incomplete in the
5442 /* Original MMX ones */
5697 /* Completely handle all MMX instructions except emms. */
6022 /* --- MMX decode failure --- */
8316 /* 0F 2A = CVTPI2PS -- convert 2 x I32 in mem/mmx to 2 x F32 in low
8390 I32 in mmx, according to prevailing SSE rounding mode */
8392 I32 in mmx, rounding towards zero */
8546 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8753 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8754 /* 0F E7 = MOVNTQ -- for us, just a plain MMX store. Note, the
8756 the FP reg tags getting trashed whenever an MMX insn happens.
8837 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8846 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8855 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8856 /* 0F C5 = PEXTRW -- extract 16-bit field from mmx(E) and put
8883 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8885 put it into the specified lane of mmx(G). */
8888 mmx reg. t4 is the new lane value. t5 is the original
8889 mmx value. t6 is the new mmx value. */
8928 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8937 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8946 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8955 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8964 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
8966 mmx(G), turn them into a byte, and put zero-extend of it in
8989 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
9048 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
9057 /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
9058 /* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */
9486 I32 in mmx, according to prevailing SSE rounding mode */
9488 I32 in mmx, rounding towards zero */
9581 /* 66 0F 2A = CVTPI2PD -- convert 2 x I32 in mem/mmx to 2 x F64 in
9588 /* Only switch to MMX mode if the source is a MMX register.
9590 convert between XMM and (M64 or MMX), which always switch
9591 to MMX mode even if 64-bit operand is M64 and not MMX. At
10104 /* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */
10307 /* F3 0F D6 = MOVQ2DQ -- move from E (mmx) to G (lo half xmm, zero
10563 /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
10863 /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
11360 /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
11481 //-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */
11789 Unsigned Bytes (MMX) */
11892 /* ***--- these are MMX class insns introduced in SSSE3 ---*** */
11894 mmx) and G to G (mmx). */
11896 mmx) and G to G (mmx). */
11897 /* 0F 38 01 = PHADDW -- 16x4 add across from E (mem or mmx) and G
11898 to G (mmx). */
11899 /* 0F 38 05 = PHSUBW -- 16x4 sub across from E (mem or mmx) and G
11900 to G (mmx). */
11901 /* 0F 38 02 = PHADDD -- 32x2 add across from E (mem or mmx) and G
11902 to G (mmx). */
11903 /* 0F 38 06 = PHSUBD -- 32x2 sub across from E (mem or mmx) and G
11904 to G (mmx). */
12044 (MMX) */
12117 /* 0F 38 08 = PSIGNB -- Packed Sign 8x8 (MMX) */
12118 /* 0F 38 09 = PSIGNW -- Packed Sign 16x4 (MMX) */
12119 /* 0F 38 09 = PSIGND -- Packed Sign 32x2 (MMX) */
12213 /* 0F 38 1C = PABSB -- Packed Absolute Value 8x8 (MMX) */
12214 /* 0F 38 1D = PABSW -- Packed Absolute Value 16x4 (MMX) */
12215 /* 0F 38 1E = PABSD -- Packed Absolute Value 32x2 (MMX) */
12301 /* 0F 3A 0F = PALIGNR -- Packed Align Right (MMX) */
12439 /* 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x8 (MMX) */
