Lines Matching full:x0100
2528 #define X0100 BITS4(0,1,0,0)
2704 case ARMalu_ADD: subopc = X0100; break;
3044 case ARMvfp_MUL: pqrs = X0100; break;
3069 case ARMvfp_MUL: pqrs = X0100; break;
3090 insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X0100,dM);
3096 insn = XXXXXXXX(0xE, X1110,X1011,X0001,dD,X1011,X0100,dM);
3141 UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM);
3151 UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM);
3246 X1011, X0100, regD);
3256 X1011, X0100, regD);
3294 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
3314 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
3552 regD, X0100, BITS4(1,Q,M,0), regM);
3556 regD, X0100, BITS4(0,Q,M,0), regM);
3664 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
3680 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
3977 X0100, BITS4(N,Q,M,0), regM);
3981 X0100, BITS4(N,Q,M,0), regM);
3985 X0100, BITS4(N,Q,M,1), regM);
3989 X0100, BITS4(N,Q,M,1), regM);
4095 #undef X0100
