Lines Matching full:accesses
27 runtime, as it masks accesses to main memory. Furthermore, the L1 caches
72 <para>Note that D1 total accesses is given by
75 accesses is given by <computeroutput>ILmr</computeroutput> +
146 <para>Cache accesses for instruction fetches are summarised
152 <para>Cache accesses for data follow. The information is similar
161 number of memory accesses, not the number of L1 misses. I.e. it is
