Lines Matching refs:l1
234 * Simple model: L1 & LL Write Through
326 * More complex model: L1 Write-through, LL Write-back
439 /* Even for a L1 hit, the write-trough L1 passes
570 /* Even for a L1 hit, the write-trough L1 passes
739 Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:LL miss */ \
946 /* FIXME (?): L1/LL line sizes must be equal ! */ \
1038 case L1_Hit: return "L1 Hit ";
1615 void cachesim_printstat(Int l1, Int l2, Int l3)
1633 commify(total[fullOffset(EG_IR) +1], l1, buf1);
1636 commify(total[fullOffset(EG_IR) +2], l1, buf1);
1645 total[fullOffset(EG_IR)], p, l1+1, buf1);
1649 total[fullOffset(EG_IR)], p, l1+1, buf1);
1663 commify( D_total[0], l1, buf1);
1669 commify( D_total[1], l1, buf1);
1675 commify( D_total[2], l1, buf1);
1687 percentify( D_total[1] * 100 * p / D_total[0], p, l1+1, buf1);
1695 percentify( D_total[2] * 100 * p / D_total[0], p, l1+1, buf1);
1716 commify(LL_total, l1, buf1);
1730 commify(LL_total_m, l1, buf1);
1737 (total[fullOffset(EG_IR)] + D_total[0]), p, l1+1, buf1);
