Lines Matching refs:op2
259 void emitInst(ARMWord op, int rd, int rn, ARMWord op2)
261 ASSERT(((op2 & ~OP2_IMM) <= 0xfff) || (((op2 & ~OP2_IMMh) <= 0xfff)));
262 m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
281 void and_r(int rd, int rn, ARMWord op2, Condition cc = AL)
283 emitInst(static_cast<ARMWord>(cc) | AND, rd, rn, op2);
286 void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL)
288 emitInst(static_cast<ARMWord>(cc) | AND | SET_CC, rd, rn, op2);
291 void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL)
293 emitInst(static_cast<ARMWord>(cc) | EOR, rd, rn, op2);
296 void eors_r(int rd, int rn, ARMWord op2, Condition cc = AL)
298 emitInst(static_cast<ARMWord>(cc) | EOR | SET_CC, rd, rn, op2);
301 void sub_r(int rd, int rn, ARMWord op2, Condition cc = AL)
303 emitInst(static_cast<ARMWord>(cc) | SUB, rd, rn, op2);
306 void subs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
308 emitInst(static_cast<ARMWord>(cc) | SUB | SET_CC, rd, rn, op2);
311 void rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL)
313 emitInst(static_cast<ARMWord>(cc) | RSB, rd, rn, op2);
316 void rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
318 emitInst(static_cast<ARMWord>(cc) | RSB | SET_CC, rd, rn, op2);
321 void add_r(int rd, int rn, ARMWord op2, Condition cc = AL)
323 emitInst(static_cast<ARMWord>(cc) | ADD, rd, rn, op2);
326 void adds_r(int rd, int rn, ARMWord op2, Condition cc = AL)
328 emitInst(static_cast<ARMWord>(cc) | ADD | SET_CC, rd, rn, op2);
331 void adc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
333 emitInst(static_cast<ARMWord>(cc) | ADC, rd, rn, op2);
336 void adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
338 emitInst(static_cast<ARMWord>(cc) | ADC | SET_CC, rd, rn, op2);
341 void sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
343 emitInst(static_cast<ARMWord>(cc) | SBC, rd, rn, op2);
346 void sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
348 emitInst(static_cast<ARMWord>(cc) | SBC | SET_CC, rd, rn, op2);
351 void rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
353 emitInst(static_cast<ARMWord>(cc) | RSC, rd, rn, op2);
356 void rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
358 emitInst(static_cast<ARMWord>(cc) | RSC | SET_CC, rd, rn, op2);
361 void tst_r(int rn, ARMWord op2, Condition cc = AL)
363 emitInst(static_cast<ARMWord>(cc) | TST | SET_CC, 0, rn, op2);
366 void teq_r(int rn, ARMWord op2, Condition cc = AL)
368 emitInst(static_cast<ARMWord>(cc) | TEQ | SET_CC, 0, rn, op2);
371 void cmp_r(int rn, ARMWord op2, Condition cc = AL)
373 emitInst(static_cast<ARMWord>(cc) | CMP | SET_CC, 0, rn, op2);
376 void cmn_r(int rn, ARMWord op2, Condition cc = AL)
378 emitInst(static_cast<ARMWord>(cc) | CMN | SET_CC, 0, rn, op2);
381 void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
383 emitInst(static_cast<ARMWord>(cc) | ORR, rd, rn, op2);
386 void orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
388 emitInst(static_cast<ARMWord>(cc) | ORR | SET_CC, rd, rn, op2);
391 void mov_r(int rd, ARMWord op2, Condition cc = AL)
393 emitInst(static_cast<ARMWord>(cc) | MOV, rd, ARMRegisters::r0, op2);
397 void movw_r(int rd, ARMWord op2, Condition cc = AL)
399 ASSERT((op2 | 0xf0fff) == 0xf0fff);
400 m_buffer.putInt(static_cast<ARMWord>(cc) | MOVW | RD(rd) | op2);
403 void movt_r(int rd, ARMWord op2, Condition cc = AL)
405 ASSERT((op2 | 0xf0fff) == 0xf0fff);
406 m_buffer.putInt(static_cast<ARMWord>(cc) | MOVT | RD(rd) | op2);
410 void movs_r(int rd, ARMWord op2, Condition cc = AL)
412 emitInst(static_cast<ARMWord>(cc) | MOV | SET_CC, rd, ARMRegisters::r0, op2);
415 void bic_r(int rd, int rn, ARMWord op2, Condition cc = AL)
417 emitInst(static_cast<ARMWord>(cc) | BIC, rd, rn, op2);
420 void bics_r(int rd, int rn, ARMWord op2, Condition cc = AL)
422 emitInst(static_cast<ARMWord>(cc) | BIC | SET_CC, rd, rn, op2);
425 void mvn_r(int rd, ARMWord op2, Condition cc = AL)
427 emitInst(static_cast<ARMWord>(cc) | MVN, rd, ARMRegisters::r0, op2);
430 void mvns_r(int rd, ARMWord op2, Condition cc = AL)
432 emitInst(static_cast<ARMWord>(cc) | MVN | SET_CC, rd, ARMRegisters::r0, op2);
490 void dtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
492 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, op2);
500 void dtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
502 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
515 void ldrh_d(int rd, int rb, ARMWord op2, Condition cc = AL)
517 emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_PRE, rd, rb, op2);
520 void ldrh_u(int rd, int rb, ARMWord op2, Condition cc = AL)
522 op2);
530 void fdtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
532 ASSERT(op2 <= 0xff);
533 emitInst(static_cast<ARMWord>(cc) | FDTR | DT_UP | (isLoad ? DT_LOAD : 0), rd, rb, op2);
536 void fdtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
538 ASSERT(op2 <= 0xff);
539 emitInst(static_cast<ARMWord>(cc) | FDTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
