| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 32 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| SparcISelLowering.cpp | 469 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
479 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
500 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
704 // Custom legalize GlobalAddress nodes into LO/HI parts.
819 case SPISD::Hi: return "SPISD::Hi"
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsJITInfo.cpp | 126 // lui $t9, %hi(NewVal)
131 int Hi = ((unsigned)NewVal & 0xffff0000) >> 16;
133 Hi++;
136 *(intptr_t *)(StubAddr) = 0xf << 26 | 25 << 16 | Hi;
171 int Hi = ((unsigned)EmittedAddr & 0xffff0000) >> 16;
173 Hi++;
176 // lui t9, %hi(EmittedAddr)
180 JCE.emitWordLE(0xf << 26 | 25 << 16 | Hi);
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| MipsISelLowering.h | 33 // No relation with Mips Hi register
34 Hi,
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| MipsISelDAGToDAG.cpp | 163 // lui $2, %hi($CPI1_0)
167 // lui $2, %hi($CPI1_0)
169 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
257 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
263 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
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| MipsISelLowering.cpp | 53 case MipsISD::Hi: return "MipsISD::Hi";
249 // Hi0: initial value of Hi register
304 Mips::HI, MVT::i32,
323 // Hi0: initial value of Hi register
378 Mips::HI, MVT::i32,
423 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
445 HI, Ty, InGlue);
[all...] |
| /external/webkit/Tools/Scripts/webkitpy/tool/bot/ |
| irc_command.py | 106 class Hi(IRCCommand):
141 "hi": Hi,
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| /external/llvm/lib/MC/ |
| SubtargetFeature.cpp | 128 const T *Hi = A + L;
130 const T *F = std::lower_bound(A, Hi, KV);
132 if (F == Hi || StringRef(F->Key) != S) return NULL;
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| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 31 Hi, ///< High address component (upper 16)
|
| SPUISelLowering.cpp | 62 bool isSigned, SDValue &Hi, const SPUTargetLowering &TLI) {
479 node_names[(unsigned) SPUISD::Hi] = "SPUISD::Hi";
613 && basePtr.getOperand(0).getOpcode() == SPUISD::Hi
958 SDValue hi = DAG.getLoad(MVT::i128, dl, the_chain, local
[all...] |
| /external/llvm/include/llvm/Support/ |
| GCOV.h | 137 uint64_t Hi = readInt();
138 uint64_t Result = Lo | (Hi << 32);
|
| MathExtras.h | 204 // get hi portion
205 uint32_t Hi = Hi_32(Value);
207 // if some bits in hi portion
208 if (Hi) {
209 // leading zeros in hi portion plus all bits in lo portion
210 Count = CountLeadingZeros_32(Hi);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
60 Hi, Lo,
|
| PPCISelDAGToDAG.cpp | 775 unsigned Hi = (Imm >> 16) & 0xFFFF;
782 // Handle the Hi bits.
783 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
784 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
789 // Just the Hi bits.
790 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
805 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
807 SDValue(Result, 0), getI32Imm(Hi));
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
31 // These routines assume that the Lo/Hi part is stored first in memory on
32 // little/big-endian machines, followed by the Hi/Lo part. This means that
35 SDValue &Lo, SDValue &Hi) {
37 GetExpandedOp(Op, Lo, Hi);
40 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
56 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
63 GetExpandedOp(InOp, Lo, Hi);
[all...] |
| LegalizeDAG.cpp | 476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
480 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
486 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
592 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
597 SDValue Lo, Hi;
604 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
609 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
622 TLI.getShiftAmountTy(Hi.getValueType()));
623 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
627 Hi.getValue(1))
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 239 SDValue Lo, Hi;
240 GetSplitVector(N->getOperand(0), Lo, Hi);
242 Hi = BitConvertToInteger(Hi);
245 std::swap(Lo, Hi);
250 JoinIntegers(Lo, Hi));
661 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
663 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
664 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
[all...] |
| LegalizeVectorTypes.cpp | 407 SDValue Lo, Hi;
418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.cpp | 120 SDValue Lo, Hi;
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
135 std::swap(Lo, Hi);
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 Hi = getCopyFromParts(DAG, DL,
149 std::swap(Lo, Hi);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi
2330 uint64_t hi = (highValue - lowBound).getZExtValue(); local
[all...] |
| /external/skia/src/core/ |
| SkMath.cpp | 110 int32_t hi = A + (B >> 16) + (lo < C); local
113 hi = -hi - Sk32ToBool(lo);
119 SkASSERT(((int32_t)lo >> 31) == hi);
123 return hi >> (shift - 32);
126 int32_t tmp = hi >> shift;
129 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
131 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit;
190 uint32_t Hi = A + (B >>16) + (Lo < C);
192 SkASSERT((Hi >> 29) == 0); // else overflo
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 201 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
203 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
609 SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
611 SDValue Ops[2] = { Lo, Hi };
646 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
648 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
663 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
665 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
[all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | 707 Expr *Hi = CR->getRHS();
708 llvm::APSInt HiVal = Hi->EvaluateKnownConstInt(Context);
712 Hi->getLocStart(),
717 Hi = ImpCastExprToType(Hi, CondType, CK_IntegralCast).take();
718 CR->setRHS(Hi);
724 Hi->getLocEnd());
848 llvm::APSInt Hi =
850 AdjustAPSInt(Hi, CondWidth, CondIsSigned);
851 while (EI != EIend && EI->first < Hi)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 560 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
563 SDValue Lo(Hi.getNode(), 1);
564 SDValue Ops[] = { Lo, Hi };
577 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
580 SDValue Lo(Hi.getNode(), 1);
581 SDValue Ops[] = { Lo, Hi };
674 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
677 SDValue Lo(Hi.getNode(), 1);
678 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
682 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl
[all...] |
