| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 193 SDValue Op0, Op1;
197 if (!SelectADDRrr(Op, Op0, Op1))
198 SelectADDRri(Op, Op0, Op1);
203 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 150 SDValue Op1 = Op.getOperand(1);
158 if (Op1.getOpcode() == ISD::Constant &&
159 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
160 cast<ConstantSDNode>(Op1)->isNullValue()) &&
163 return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 288 SDValue Op0, Op1;
292 if (!SelectAddr(Op, Op0, Op1))
298 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 245 SDValue Op1 = Node->getOperand(0);
251 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 530 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
532 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(),
541 if (Value *V = dyn_castNegVal(Op1)) {
549 return BinaryOperator::CreateXor(Op0, Op1);
553 return BinaryOperator::CreateNot(Op1);
558 if (match(Op1, m_Not(m_Value(X))))
565 if (match(Op1, m_LShr(m_Value(X), m_ConstantInt(CI))) &&
570 if (match(Op1, m_AShr(m_Value(X), m_ConstantInt(CI))) &&
577 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
582 if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1))
[all...] |
| InstCombineMulDivRem.cpp | 101 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
103 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
109 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X
112 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
164 if (isa<Constant>(Op1)) {
176 if (Value *Op1v = dyn_castNegVal(Op1))
182 Value *Op1C = Op1;
188 BO = dyn_cast<BinaryOperator>(Op1);
220 return BinaryOperator::CreateAnd(Op0, Op1);
227 return BinaryOperator::CreateShl(Op1, Y)
[all...] |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1))
44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
48 Op1->getName());
311 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
319 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
324 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
335 if (Op1->uge(TypeBits))
[all...] |
| InstCombineCalls.cpp | 256 Value *Op1 = II->getArgOperand(0)->stripPointerCasts();
262 if (GEPOperator *GEP = dyn_cast<GEPOperator>(Op1)) {
270 Op1 = GEP->getPointerOperand()->stripPointerCasts();
274 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(Op1))
280 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(Op1)) {
289 } else if (AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
299 } else if (CallInst *MI = extractMallocCall(Op1)) {
641 Value *Op1 = Builder->CreateBitCast(II->getArgOperand(1),
657 Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1,
[all...] |
| InstCombineCasts.cpp | [all...] |
| InstCombineAndOrXor.cpp | 728 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
731 return getICmpValue(isSigned, Code, Op0, Op1, Builder);
[all...] |
| InstCombineCompares.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 392 SDValue Op1 = Op.getOperand(1);
407 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
414 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
416 return DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
|
| FastISel.cpp | 346 unsigned Op1 = getRegForValue(I->getOperand(1));
347 if (Op1 == 0) return false;
351 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
400 unsigned Op1 = getRegForValue(I->getOperand(1));
401 if (Op1 == 0)
411 Op1, Op1IsKill);
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 129 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
130 if (Op1->getOpcode() == OpcodeToExpand) {
132 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
168 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS);
171 !Op1 || Op1->getOpcode() != OpcodeToExtract)
176 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1);
241 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)
[all...] |
| ValueTracking.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| ELFWriter.cpp | 568 // solve direclty using a relocation entry. GlobalValue=Op0, CstInt=Op1
572 const Constant *Op1 = CE->getOperand(1);
573 assert(isa<ConstantInt>(Op1) && "Op1 must be a ConstantInt");
578 const APInt &RHS = cast<ConstantInt>(Op1)->getValue();
[all...] |
| RegisterCoalescer.cpp | 664 unsigned Op1, Op2, NewDstIdx;
665 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
667 if (Op1 == UseOpIdx)
670 NewDstIdx = Op1;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 377 SDValue Op1 = N->getOperand(1);
382 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
389 unsigned Op1Opc = Op1.getOpcode();
399 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
400 Op1.getOperand(0).getOpcode() != ISD::SRL) {
401 std::swap(Op0, Op1);
407 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
408 Op1.getOperand(0).getOpcode() != ISD::SRL) {
409 std::swap(Op0, Op1);
420 isInt32Immediate(Op1.getOperand(1), Value))
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 270 SDValue Op0, Op1;
274 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
275 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
276 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
279 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
280 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
282 Op1 = getSmallIPtrImm(0);
289 SelectAddrIdxOnly(Op, Op, Op0, Op1);
295 OutOps.push_back(Op1);
422 const SDValue Op1 = N.getOperand(1)
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 866 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
868 if (isSrcOp(*Op1) && Op2->isReg()) {
885 delete Op1;
896 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
898 if (isDstOp(*Op2) && Op1->isReg()) {
900 unsigned reg = Op1->getReg();
915 delete Op1;
930 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
931 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 117 unsigned Op1, bool Op1IsKill);
121 unsigned Op1, bool Op1IsKill,
134 unsigned Op1, bool Op1IsKill,
309 unsigned Op1, bool Op1IsKill) {
316 .addReg(Op1, Op1IsKill * RegState::Kill));
320 .addReg(Op1, Op1IsKill * RegState::Kill));
331 unsigned Op1, bool Op1IsKill,
339 .addReg(Op1, Op1IsKill * RegState::Kill)
344 .addReg(Op1, Op1IsKill * RegState::Kill)
400 unsigned Op1, bool Op1IsKill
[all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 875 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
881 if (isa<ConstantPointerNull>(Op1))
882 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
887 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
899 unsigned Op1Reg = getRegForValue(Op1);
917 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
[all...] |
| X86ISelDAGToDAG.cpp | 321 SDValue Op1 = U->getOperand(1);
333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
347 if (Op1.getOpcode() == X86ISD::Wrapper) {
348 SDValue Val = Op1.getOperand(0);
[all...] |
