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    Searched defs:Orders (Results 1 - 2 of 2) sorted by null

  /external/llvm/utils/TableGen/
CodeGenRegisters.h 90 // Allocation orders. Order[0] always contains all registers in Members.
91 std::vector<SmallVector<Record*, 16> > Orders;
176 return Orders[No];
179 // Return the total number of allocation orders available.
180 unsigned getNumOrders() const { return Orders.size(); }
  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 636 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
654 Orders.push_back(std::make_pair(DVOrder, DbgMI));
668 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
674 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
681 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
685 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
686 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
695 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
736 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
743 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
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