OpenGrok
Home
Sort by relevance
Sort by last modified time
Full Search
Definition
Symbol
File Path
History
|
|
Help
Searched
defs:Registers
(Results
1 - 8
of
8
) sorted by null
/external/llvm/utils/TableGen/
CodeGenRegisters.h
47
// Get a map of sub-
registers
computed lazily.
48
// This includes unique entries for all sub-sub-
registers
.
52
assert(SubRegsComplete && "Must precompute sub-
registers
");
56
// Add sub-
registers
to OSet following a pre-order defined by the .td file.
59
// List of super-
registers
in topological order, small to large.
62
// Get the list of super-
registers
.
63
// This is only valid after computeDerivedInfo has visited all
registers
.
65
assert(SubRegsComplete && "Must precompute sub-
registers
");
90
// Allocation orders. Order[0] always contains all
registers
in Members.
143
// 1. All RC
registers
are also in this
[
all
...]
RegisterInfoEmitter.cpp
28
// runEnums - Print out enum values for all of the
registers
.
32
const std::vector<CodeGenRegister*> &
Registers
= Bank.getRegisters();
34
std::string Namespace =
Registers
[0]->TheDef->getValueAsString("Namespace");
50
for (unsigned i = 0, e =
Registers
.size(); i != e; ++i)
51
OS << " " <<
Registers
[i]->getName() << " = " <<
52
Registers
[i]->EnumValue << ",\n";
53
assert(
Registers
.size() ==
Registers
[
Registers
.size()-1]->EnumValue &&
55
OS << " NUM_TARGET_REGS \t// " <<
Registers
.size()+1 << "\n"
[
all
...]
AsmWriterEmitter.cpp
464
const std::vector<CodeGenRegister*> &
Registers
) {
467
for (unsigned i = 0, e =
Registers
.size(); i != e; ++i) {
468
const CodeGenRegister &Reg = *
Registers
[i];
519
const std::vector<CodeGenRegister*> &
Registers
=
533
O << " assert(RegNo && RegNo < " << (
Registers
.size()+1)
539
emitRegisterNameString(O, AltNameIndices[i]->getName(),
Registers
);
541
emitRegisterNameString(O, "",
Registers
);
[
all
...]
AsmMatcherEmitter.cpp
175
/// For register classes, the records for all the
registers
in this class.
176
std::set<Record*>
Registers
;
196
//
Registers
classes are only related to
registers
classes, and only if
204
std::set_intersection(
Registers
.begin(),
Registers
.end(),
205
RHS.
Registers
.begin(), RHS.
Registers
.end(),
661
// Collect singleton
registers
, if used.
915
const std::vector<CodeGenRegister*> &
Registers
[
all
...]
/external/grub/netboot/
3c90x.c
54
enum
Registers
83
/** following are windowed
registers
**/
771
/** Program the MAC address into the station address
registers
**/
/external/v8/src/arm/
constants-arm.h
94
// Number of
registers
in normal ARM mode.
442
// These constants are declared in assembler-arm.cc, as they use named
registers
739
class
Registers
{
/external/v8/src/mips/
constants-mips.h
61
//
Registers
and FPURegister.
63
// Number of general purpose
registers
.
67
// Number of
registers
with HI, LO, and pc.
73
// Number coprocessor
registers
.
77
// FPU (coprocessor 1) control
registers
. Currently only FCSR is implemented.
87
class
Registers
{
488
//
registers
and other constants.
/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp
276
SmallVector<unsigned, 8>
Registers
;
316
// A vector register list is a sequential list of 1 to 4
registers
.
402
Registers
= o.
Registers
;
484
return
Registers
;
779
// Thumb reg+reg addressing is simple. Just two
registers
, a base and
[
all
...]
Completed in 325 milliseconds