HomeSort by relevance Sort by last modified time
    Searched defs:Regs (Results 1 - 8 of 8) sorted by null

  /external/llvm/utils/TableGen/
CodeGenTarget.cpp 175 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters();
176 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
177 if (Regs[i]->TheDef->getValueAsString("AsmName") == Name)
178 return Regs[i];
RegisterInfoEmitter.cpp 99 const std::vector<CodeGenRegister*> &Regs,
108 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
109 Record *Reg = Regs[i]->TheDef;
162 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163 Record *Reg = Regs[i]->TheDef;
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
265 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
266 const CodeGenRegister *Reg = Regs[i];
282 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
283 const CodeGenRegister &Reg = *Regs[i]
    [all...]
CodeGenRegisters.cpp 523 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
524 std::sort(Regs.begin(), Regs.end(), LessRecord());
525 Registers.reserve(Regs.size());
527 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
528 getReg(Regs[i]);
AsmMatcherEmitter.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 551 SmallVector<std::pair<unsigned,bool>, 4> Regs;
579 Regs.push_back(std::make_pair(Reg, isKill));
582 if (Regs.empty())
584 if (Regs.size() > 1 || StrOpc== 0) {
588 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
589 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
590 } else if (Regs.size() == 1) {
593 .addReg(Regs[0].first, getKillRegState(Regs[0].second)
    [all...]
ARMLoadStoreOptimizer.cpp 93 DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
286 /// registers in Regs as the register operands that would be loaded / stored.
294 SmallVector<std::pair<unsigned, bool>, 8> &Regs) {
296 unsigned NumRegs = Regs.size();
326 NewBase = Regs[NumRegs-1].first;
359 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
360 | getKillRegState(Regs[i].second));
395 SmallVector<std::pair<unsigned, bool>, 8> Regs;
401 Regs.push_back(std::make_pair(Reg, isKill));
408 Pred, PredReg, Scratch, dl, Regs))
    [all...]
  /external/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 704 SmallPtrSet<const SCEV *, 16> &Regs,
715 SmallPtrSet<const SCEV *, 16> &Regs,
719 SmallPtrSet<const SCEV *, 16> &Regs,
728 SmallPtrSet<const SCEV *, 16> &Regs,
761 if (!Regs.count(AR->getStart())) {
762 RateRegister(AR->getStart(), Regs, L, SE, DT);
771 if (!Regs.count(AR->getOperand(1))) {
772 RateRegister(AR->getOperand(1), Regs, L, SE, DT);
796 SmallPtrSet<const SCEV *, 16> &Regs,
799 if (Regs.insert(Reg)
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 568 /// Regs - This list holds the registers assigned to the values.
572 SmallVector<unsigned, 4> Regs;
576 RegsForValue(const SmallVector<unsigned, 4> &regs,
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
589 Regs.push_back(Reg + i);
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT)
    [all...]

Completed in 338 milliseconds