| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 74 MVT ArgVT = Ins[i].VT;
92 MVT VT = Outs[i].VT;
94 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
106 MVT VT = Outs[i].VT;
108 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
111 << EVT(VT).getEVTString()
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 54 EVT VT = MVT::i32;
69 Loads[i] = DAG.getLoad(VT, dl, Chain,
101 VT = MVT::i16;
104 VT = MVT::i8;
108 Loads[i] = DAG.getLoad(VT, dl, Chain,
123 VT = MVT::i16;
126 VT = MVT::i8;
|
| PTXISelDAGToDAG.cpp | 113 EVT VT = Node->getValueType(0);
114 assert(VT.isSimple() && "READ_PARAM only implemented for MVT types");
116 MVT Type = VT.getSimpleVT();
138 return CurDAG->getMachineNode(OpCode, dl, VT, Ops, 4);
151 EVT VT = Value->getValueType(0);
152 assert(VT.isSimple() && "WRITE_PARAM only implemented for MVT types");
154 MVT Type = VT.getSimpleVT();
|
| /external/llvm/utils/TableGen/ |
| CallingConvEmitter.cpp | 72 Record *VT = VTs->getElementAsRecord(i);
74 O << "LocVT == " << getEnumName(getValueType(VT));
|
| DAGISelMatcher.cpp | 208 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n';
213 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n';
222 OS << " VT=" << VT << '\n';
291 return HashString(Val) ^ VT;
|
| CodeGenTarget.cpp | 409 MVT::SimpleValueType VT;
414 VT = OverloadedVTs[MatchTy];
420 VT == MVT::iAny || VT == MVT::vAny) &&
423 VT = getValueType(TyEl->getValueAsDef("VT"));
425 if (EVT(VT).isOverloaded()) {
426 OverloadedVTs.push_back(VT);
431 if (VT == MVT::isVoid)
434 IS.RetVTs.push_back(VT);
[all...] |
| IntrinsicEmitter.cpp | 177 static void EmitTypeForValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
178 if (EVT(VT).isInteger()) {
179 unsigned BitWidth = EVT(VT).getSizeInBits();
181 } else if (VT == MVT::Other) {
184 } else if (VT == MVT::f32) {
186 } else if (VT == MVT::f64) {
188 } else if (VT == MVT::f80) {
190 } else if (VT == MVT::f128) {
192 } else if (VT == MVT::ppcf128) {
194 } else if (VT == MVT::isVoid)
[all...] |
| DAGISelMatcherGen.cpp | 27 MVT::SimpleValueType VT = MVT::Other;
38 VT = RC.getValueTypeNum(0);
43 assert(VT == RC.getValueTypeNum(0));
45 return VT;
[all...] |
| /external/clang/include/clang/AST/ |
| DeclContextInternals.h | 155 DeclsTy *VT = new DeclsTy();
156 VT->push_back(OldD);
157 Data = VT;
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
98 VT = MVT::i16;
101 VT = MVT::i8;
105 Loads[i] = DAG.getLoad(VT, dl, Chain,
120 VT = MVT::i16;
123 VT = MVT::i8;
|
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 29 EVT VT;
30 VT.LLVMTy = IntegerType::get(Context, BitWidth);
31 assert(VT.isExtended() && "Type is not extended!");
32 return VT;
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT,
38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 85 EVT VT = Node->getValueType(ResNo);
88 if (TLI->isTypeLegal(VT))
89 UseRC = TLI->getRegClassFor(VT);
110 EVT VT = Node->getValueType(Op.getResNo());
111 if (VT == MVT::Other || VT == MVT::Glue)
138 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
144 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
147 DstRC = TLI->getRegClassFor(VT);
401 EVT VT, DebugLoc DL)
[all...] |
| SelectionDAGPrinter.cpp | 96 EVT VT = Op.getValueType();
97 if (VT == MVT::Glue)
99 else if (VT == MVT::Other)
|
| FunctionLoweringInfo.cpp | 170 EVT VT = ValueVTs[vti];
171 unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT);
208 unsigned FunctionLoweringInfo::CreateReg(EVT VT) {
209 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
270 "PHIs with non-vector integer types should have a single VT.");
|
| LegalizeTypesGeneric.cpp | 375 EVT VT = N->getValueType(0);
376 assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
378 unsigned NumElts = VT.getVectorNumElements();
384 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
|
| LegalizeVectorOps.cpp | 275 EVT VT = Op.getValueType();
278 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
291 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
388 EVT VT = Op.getOperand(0).getValueType();
397 if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
398 !TLI.isOperationLegalOrCustom(ISD::XOR, VT) ||
399 !TLI.isOperationLegalOrCustom(ISD::OR, VT))
402 assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
407 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
408 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2)
[all...] |
| ScheduleDAGFast.cpp | 218 EVT VT = N->getValueType(i);
219 if (VT == MVT::Glue)
221 else if (VT == MVT::Other)
226 EVT VT = Op.getNode()->getValueType(Op.getResNo());
227 if (VT == MVT::Glue)
569 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
571 TRI->getMinimalPhysRegClass(Reg, VT);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 211 EVT VT = Node->getValueType(0);
212 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
| /external/clang/lib/CodeGen/ |
| CodeGenTypes.cpp | 445 const VectorType *VT = cast<VectorType>(Ty);
446 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()),
447 VT->getNumElements());
|
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 109 MVT VT;
112 InputArg() : VT(MVT::Other), Used(false) {}
113 InputArg(ArgFlagsTy flags, EVT vt, bool used)
115 VT = vt.getSimpleVT();
125 MVT VT;
131 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed)
133 VT = vt.getSimpleVT();
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 231 EVT VT = LHS.getValueType();
232 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
233 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
236 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 240 EVT VT = (strcmp(Modifier+6,"64") == 0) ?
243 Reg = getX86SubSuperRegister(Reg, VT);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 395 EVT VT = Addr.getValueType();
398 AM12.Base.Reg = CurDAG->getRegister(0, VT);
438 EVT VT = Addr.getValueType();
441 AM.Base.Reg = CurDAG->getRegister(0, VT);
486 EVT VT = Addr.getValueType();
489 AM12.Base.Reg = CurDAG->getRegister(0, VT);
493 AM12.IndexReg = CurDAG->getRegister(0, VT);
530 EVT VT = Addr.getValueType();
533 AM.Base.Reg = CurDAG->getRegister(0, VT);
537 AM.IndexReg = CurDAG->getRegister(0, VT);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 222 EVT VT) const {
228 if (VT == MVT::i8)
235 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
596 EVT VT = Op.getValueType();
606 VT, N->getOperand(0), N->getOperand(1));
609 VT, N->getOperand(0), N->getOperand(1));
612 VT, N->getOperand(0), N->getOperand(1));
625 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
631 dl, VT, Victim);
820 EVT VT = Op.getValueType()
[all...] |
| /external/clang/lib/Sema/ |
| SemaExprMember.cpp | 356 QualType VT = S.Context.getExtVectorType(vecType->getElementType(), CompSize);
363 if ((*I)->getUnderlyingType() == VT)
367 return VT; // should never get here (a typedef type should always be found).
[all...] |
