| /libcore/luni/src/main/java/libcore/net/http/ |
| ResponseSource.java | 22 * Return the response from the cache immediately.
24 CACHE,
27 * Make a conditional request to the host, returning the cache response if
28 * the cache is valid and the network response otherwise.
|
| HttpEngine.java | 60 * <p>The request and response may be served by the HTTP response cache, by the
155 /** Null until a response is received from the network or the cache */
159 * The cache response currently being validated on a conditional get. Null
225 this.responseSource = ResponseSource.CACHE;
268 if (responseSource == ResponseSource.CACHE) {
436 // Should we cache this response for this request?
441 // Offer this request to the cache.
467 // If the response body comes from the cache, close it.
635 * neither needed nor known when querying the response cache.
|
| ResponseHeaders.java | 69 * In the response, this field's name "no-cache" is misleading. It doesn't
88 * this directive is not honored by this cache.
95 * wants to make a request if it can be fully satisfied by the cache.
120 if (directive.equalsIgnoreCase("no-cache")) {
139 if ("Cache-Control".equalsIgnoreCase(fieldName)) {
150 if (value.equalsIgnoreCase("no-cache")) {
432 return ResponseSource.CACHE;
461 * cached response, we may return the cache's response. Like Chrome (but
|
| HttpResponseCache.java | 57 * Cache responses in a directory on the file system. Most clients should use
62 // TODO: add APIs to iterate the cache?
68 private final DiskLruCache cache; field in class:HttpResponseCache
78 cache = DiskLruCache.open(directory, VERSION, ENTRY_COUNT, maxSize);
97 snapshot = cache.get(key);
103 // Give up because the cache cannot be read.
144 cache.remove(key);
146 // The cache cannot be written.
151 * Don't cache non-GET responses. We're technically allowed to cache
[all...] |
| /external/chromium/chrome/browser/extensions/ |
| image_loading_tracker.h | 41 CACHE,
67 // if the image was found in the cache.
71 CacheParam cache);
102 // If LoadImage is told to cache the result an entry is added here. The
|
| image_loading_tracker_unittest.cc | 97 // Tests asking ImageLoadingTracker to cache pushes the result to the Extension.
98 TEST_F(ImageLoadingTrackerTest, Cache) {
111 ImageLoadingTracker::CACHE);
135 ImageLoadingTracker::CACHE);
157 ImageLoadingTracker::CACHE);
|
| extension_icon_manager.cc | 58 ImageLoadingTracker::CACHE);
|
| extension_tab_helper.cc | 145 ImageLoadingTracker::CACHE);
|
| image_loading_tracker.cc | 138 CacheParam cache) {
156 if (cache == CACHE) {
191 // we don't attempt to cache the image when the load completes.
|
| /external/kernel-headers/original/linux/ |
| slab.h | 18 #include <asm/cache.h> /* kmalloc_sizes.h needs L1_CACHE_BYTES */
30 #define SLAB_NO_GROW __GFP_NO_GROW /* don't grow a cache */
38 #define SLAB_RED_ZONE 0x00000400UL /* Red zone objs in a cache */
40 #define SLAB_HWCACHE_ALIGN 0x00002000UL /* align objs on a h/w cache lines */
115 * %__GFP_COLD - Request cache-cold pages instead of
116 * trying to return cache-warm pages.
138 #define CACHE(x) \
144 #undef CACHE
168 #define CACHE(x) \
174 #undef CACHE
[all...] |
| /external/chromium/chrome/browser/sidebar/ |
| sidebar_container.cc | 70 ImageLoadingTracker::CACHE);
|
| /external/qemu/android/avd/ |
| info.h | 38 * it may also contain other lines that cache stuff found in the
61 _AVD_IMG(CACHE,"cache.img","cache") \
84 /* use to ignore the cache partition */
86 /* use to wipe cache partition, ignored if NO_CACHE is set */
149 /* This function returns NULL if the cache image file cannot be found.
|
| /external/chromium/chrome/browser/profiles/ |
| profile_impl_io_data.cc | 222 BrowserThread::GetMessageLoopProxyForThread(BrowserThread::CACHE));
239 BrowserThread::GetMessageLoopProxyForThread(BrowserThread::CACHE));
303 // TODO(creis): Determine correct cache size.
311 // Use a separate HTTP disk cache for isolated apps.
317 BrowserThread::GetMessageLoopProxyForThread(BrowserThread::CACHE));
|
| /device/samsung/crespo/sec_mm/sec_omx/sec_codecs/video/mfc_c110/include/ |
| SsbSipMfcApi.h | 65 CACHE = 1
|
| /external/qemu/block/ |
| vpc.c | 33 //#define CACHE
125 #ifdef CACHE
218 #ifdef CACHE
273 #ifdef CACHE
606 #ifdef CACHE
|
| /external/chromium/chrome/browser/metrics/ |
| thread_watcher.cc | 252 if (BrowserThread::IsMessageLoopValid(BrowserThread::CACHE)) {
253 ThreadWatcher::StartWatching(BrowserThread::CACHE, "CACHE", kSleepTime,
|
| /external/grub/stage2/ |
| fsys_reiserfs.c | 293 /* The size of the node cache */
345 #define CACHE(i) (ROOT + ((i) << INFO->fullblocksize_shift))
346 #define LEAF CACHE (DISK_LEAF_NODE_LEVEL)
348 #define BLOCKHEAD(cache) ((struct block_head *) cache)
350 #define KEY(cache) ((struct key *) ((int) cache + BLKH_SIZE))
351 #define DC(cache) ((struct disk_child *) \
352 ((int) cache + BLKH_SIZE + KEY_SIZE * nr_item))
358 * The journal cache. For each transaction it contains the number o
694 char* cache = CACHE(depth); local
732 char *cache; local
822 char *cache; local
[all...] |
| /external/chromium/chrome/browser/ |
| background_application_list_model.cc | 136 ImageLoadingTracker::CACHE);
|
| browser_process_impl.cc | 782 new BrowserThread(BrowserThread::CACHE));
[all...] |
| /external/bison/djgpp/ |
| config.bat | 52 Rem Special arguments are: NLS, XSRC, CACHE, STATIC_LIBS, LIBICONV_PREFIX, LIBINTL_PREFIX and DEPS.
68 if "%1" == "cache" goto NextArgument
69 if "%1" == "CACHE" goto NextArgument
70 if "%1" == "no-cache" goto NoCaching
71 if "%1" == "no-CACHE" goto NoCaching
72 if "%1" == "NO-CACHE" goto NoCaching
75 if "%1" == "no-cache" set CACHING=disabled
76 if "%1" == "no-CACHE" set CACHING=disabled
77 if "%1" == "NO-CACHE" set CACHING=disabled
147 if "%CACHING%" == "enabled" echo --cache-file=%XSRC%/djgpp/config.cache >> arguments
[all...] |
| /device/samsung/crespo/sec_mm/sec_omx/sec_codecs/video/mfc_c110/dec/src/ |
| SsbSipMfcDecAPI.c | 109 *(unsigned int *)value == CACHE) {
|
| /external/oprofile/events/mips/24K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
39 event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 24K family microarchitecture)
55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
57 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/oprofile/events/mips/34K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
39 event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
61 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
39 event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
55 event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache mis
[all...] |
| /device/samsung/crespo/sec_mm/sec_omx/sec_codecs/video/mfc_c110/enc/src/ |
| SsbSipMfcEncAPI.c | 55 *(unsigned int *)value == CACHE) {
|
