| /external/elfutils/libdw/ |
| dwarf_getloclist.c | 232 case DW_OP_regx:
|
| dwarf.h | 345 DW_OP_regx = 0x90, /* Unsigned LEB128 register. */
|
| /external/llvm/lib/Support/ |
| Dwarf.cpp | 428 case DW_OP_regx: return "DW_OP_regx";
[all...] |
| /external/valgrind/main/coregrind/m_debuginfo/ |
| d3basics.c | 518 && expr[0] == DW_OP_regx) {
525 FAIL("evaluate_Dwarf3_Expr: DW_OP_regx*: invalid expr size");
635 case DW_OP_regx:
[all...] |
| priv_d3basics.h | 530 DW_OP_regx = 0x90,
|
| /external/llvm/include/llvm/Support/ |
| Dwarf.h | 439 DW_OP_regx = 0x90,
|
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 241 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
242 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
248 OutStreamer.AddComment("DW_OP_regx for S register");
249 EmitInt8(dwarf::DW_OP_regx);
268 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
275 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
276 EmitInt8(dwarf::DW_OP_regx);
282 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
283 EmitInt8(dwarf::DW_OP_regx);
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfCompileUnit.cpp | 217 addUInt(TheDie, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_regx);
402 addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_regx);
[all...] |
| AsmPrinter.cpp | 830 OutStreamer.AddComment("DW_OP_regx");
831 EmitInt8(dwarf::DW_OP_regx);
[all...] |
| /external/qemu/elff/ |
| dwarf.h | 582 #define DW_OP_regx 0x90
[all...] |
| /ndk/sources/host-tools/ndk-stack/elff/ |
| dwarf.h | 582 #define DW_OP_regx 0x90
[all...] |
| /external/elfutils/src/ |
| readelf.c | [all...] |
