| /external/llvm/include/llvm/CodeGen/ |
| CalcSpillWeights.h | 44 LiveIntervals &LIS;
48 VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
50 MF(mf), LIS(lis), Loops(loops) {}
|
| LiveInterval.h | 317 void RenumberValues(LiveIntervals &lis);
560 /// // allocate numComps-1 new LiveIntervals into LIS[1..]
561 /// ConEQ.Distribute(LIS);
565 LiveIntervals &LIS;
574 explicit ConnectedVNInfoEqClasses(LiveIntervals &lis) : LIS(lis) {}
|
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 33 LiveIntervals &LIS,
39 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
56 void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
72 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
76 scanRemattable(lis, tii, aa);
85 LiveIntervals &lis) {
93 if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
101 LiveInterval &li = lis.getInterval(MO.getReg());
114 LiveIntervals &lis) {
[all...] |
| RegisterCoalescer.cpp | 87 LiveIntervals *LIS;
419 if (!LIS->hasInterval(CP.getDstReg()))
423 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
425 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
426 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getDefIndex();
482 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
496 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
499 LIS->getInterval(*AS).print(dbgs(), TRI);
526 if (!LIS->hasInterval(*SR)
[all...] |
| InlineSpiller.cpp | 56 LiveIntervals &LIS;
141 LIS(pass.getAnalysis<LiveIntervals>()),
234 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
284 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
370 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
388 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
528 LiveInterval &LI = LIS.getInterval(Reg);
529 LiveInterval &OrigLI = LIS.getInterval(Original);
574 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
580 LiveInterval &SrcLI = LIS.getInterval(SrcReg)
[all...] |
| LiveDebugVariables.cpp | 129 LiveIntervals &LIS, const TargetInstrInfo &TII);
223 /// @param LIS Live intervals analysis.
228 LiveIntervals &LIS, MachineDominatorTree &MDT,
242 LiveIntervals &LIS);
247 LiveIntervals &LIS, MachineDominatorTree &MDT,
264 LiveIntervals &LIS, const TargetInstrInfo &TRI);
284 LiveIntervals *LIS;
470 LIS->getMBBStartIdx(MBB) :
471 LIS->getInstructionIndex(llvm::prior(MBBI)).getDefIndex();
488 LiveIntervals &LIS, MachineDominatorTree &MDT
[all...] |
| SplitKit.cpp | 43 const LiveIntervals &lis,
47 LIS(lis),
71 LSP.first = LIS.getMBBEndIdx(MBB);
73 LSP.first = LIS.getInstructionIndex(FirstTerm);
84 LSP.second = LIS.getInstructionIndex(I);
92 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
115 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
132 const_cast<LiveIntervals&>(LIS)
163 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start)
[all...] |
| LiveRangeEdit.h | 75 void scanRemattable(LiveIntervals &lis,
82 SlotIndex UseIdx, LiveIntervals &lis);
133 LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) {
134 return createFrom(getReg(), LIS, VRM);
161 LiveIntervals &lis);
188 /// to erase it from LIS.
189 void eraseVirtReg(unsigned Reg, LiveIntervals &LIS);
|
| CalcSpillWeights.cpp | 48 LiveIntervals &lis = getAnalysis<LiveIntervals>(); local
49 VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>());
50 for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) {
132 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
146 if (hweight > bestPhys && LIS.isAllocatable(hint))
168 if (li.isZeroLength(LIS.getSlotIndexes())) {
179 if (LIS.isReMaterializable(li, 0, isLoad)) {
|
| RegAllocBase.h | 94 LiveIntervals *LIS;
102 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
107 void init(VirtRegMap &vrm, LiveIntervals &lis);
|
| RegAllocBasic.cpp | 200 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
230 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
235 LIS = &lis;
266 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
307 LIS->removeInterval(VirtReg->reg);
352 LIS->removeInterval(SplitVirtReg->reg);
432 SlotIndexes *Indexes = LIS->getSlotIndexes()
[all...] |
| SplitKit.h | 45 const LiveIntervals &LIS;
119 SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
205 LiveIntervals &LIS;
|
| RegAllocGreedy.cpp | 360 unassign(LIS->getInterval(VirtReg), PhysReg);
374 LiveInterval &LI = LIS->getInterval(VirtReg);
433 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
[all...] |
| LiveInterval.cpp | 149 void LiveInterval::RenumberValues(LiveIntervals &lis) {
678 const MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
684 LI->getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot()))
718 SlotIndex Idx = LIS.getInstructionIndex(MI);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 377 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
590 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
669 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
[all...] |
| PPCRegisterInfo.cpp | 292 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
603 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
|
| PPCISelLowering.cpp | [all...] |
