/external/llvm/include/llvm/MC/ |
MCInstrItineraries.h | 154 /// getStageLatency - Return the total stage latency of the given 155 /// class. The latency is the maximum completion time for any stage 164 // be used for zero-latency pseudo ops. 169 unsigned Latency = 0, StartCycle = 0; 172 Latency = std::max(Latency, StartCycle + IS->getCycles()); 176 return Latency; 217 /// getOperandLatency - Compute and return the use operand latency of a given
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/external/llvm/include/llvm/CodeGen/ |
ScheduleDAG.h | 83 /// Latency - The time associated with this edge. Often this is just 84 /// the value of the Latency field of the predecessor, however advanced 86 unsigned Latency; 95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 98 : Dep(S, kind), Contents(), Latency(latency) { 120 if (Dep != Other.Dep || Latency != Other.Latency) return false; 140 /// getLatency - Return the latency value for this edge, which roughly 145 return Latency; [all...] |
/external/llvm/lib/CodeGen/ |
ScheduleDAGInstrs.cpp | 153 /// especially important when the definition latency of the return value(s) 249 // Assign the Latency field of SU using target-provided information. 251 SU->Latency = 1; 268 // dependencies we use a latency of 0 because for a multi-issue 271 // TODO: Using a latency of 1 here for output dependencies assumes 299 unsigned DataLatency = SU->Latency; 305 // Optionally add in a special extra latency for nodes that 323 // Adjust the dependence latency using operand def/use 366 unsigned Latency = SU->Latency; [all...] |
CriticalAntiDepBreaker.cpp | 168 // In the case of a latency tie, prefer an anti-dependency edge over 437 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 443 DEBUG(dbgs() << "Critical path has total latency " 444 << (Max->getDepth() + Max->Latency) << "\n");
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AggressiveAntiDepBreaker.cpp | 304 // In the case of a latency tie, prefer an anti-dependency edge over 755 ((SU->getDepth() + SU->Latency) > 756 (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) { [all...] |
ScheduleDAG.cpp | 301 dbgs() << " Latency : " << Latency << "\n"; 320 dbgs() << ": Latency=" << I->getLatency(); 341 dbgs() << ": Latency=" << I->getLatency();
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.cpp | 38 // This allows latency based scheduler to notice high latency instructions 40 // balancing scheduler heursitics than with the actual machine latency. 42 "sched-high-latency-cycles", cl::Hidden, cl::init(10), 43 cl::desc("Roughly estimate the number of cycles that 'long latency'" 84 SU->Latency = Old->Latency; 346 // Schedule zero-latency TokenFactor below any nodes that may increase the 362 // Assign the Latency field of NodeSUnit using target-provided information. 442 // If this is a ctrl dep, latency is 1 [all...] |
ScheduleDAGList.cpp | 56 /// been issued, but their results are not ready yet (due to the latency of 188 assert(PendingQueue[i]->getDepth() > CurCycle && "Negative latency?"); 231 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
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ScheduleDAGFast.cpp | 334 AddPred(NewSU, SDep(LoadSU, SDep::Order, LoadSU->Latency)); 411 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg)); 412 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0)); 594 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1, 603 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
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ScheduleDAGRRList.cpp | 60 "which tries to balance latency and register pressure", 128 /// NeedLatency - True if the scheduler will make use of latency information. 136 /// been issued, but their results are not ready yet (due to the latency of 272 /// need actual latency information but the hybrid scheduler does. 485 // Bypass lots of virtual calls in case of long latency. 510 // But given the crude nature of modeling latency though such nodes, we 516 // Bump CurCycle to account for latency. We assume the latency of other 645 // Check AvailableQueue after ReleasePredecessors in case of zero latency. 919 AddPred(NewSU, SDep(LoadSU, SDep::Data, LoadSU->Latency)); [all...] |
SelectionDAGISel.cpp | 147 if (TLI.getSchedulingPreference() == Sched::Latency) [all...] |
TargetLowering.cpp | 613 SchedPreferenceInfo = Sched::Latency; [all...] |
/external/llvm/include/llvm/Target/ |
TargetMachine.h | 59 Latency, // Scheduling for shortest total latency. 61 Hybrid, // Scheduling for both latency and register pressure.
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/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.cpp | [all...] |
ARMISelLowering.cpp | [all...] |
/external/oprofile/events/mips/1004K/ |
events | 95 event:0x3d counters:0 um:zero minimum:500 name:SELF_INTERVENTION_LATENCY : 61-0 Latency from miss detection to self intervention 96 event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned
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/external/blktrace/btt/doc/ |
btt.tex | 463 \item[iostat] Latency information -- both Q2d, D2c and Q2C -- 676 \newpage\section{\label{sec:lat}\label{sec:lat-q2d}\label{sec:lat-q2c}\label{sec:lat-d2c}Latency Data Files} 678 The latency data files which can be optionally produced by \texttt{btt} 679 provide per-IO latency information, one for queue time (Q2D), one 684 while the second column (Y values) shows the actual latency for a [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 83 setSchedulingPreference(Sched::Latency); [all...] |